From 86975f4e54cf95e7890187e2e8796b3cc872a043 Mon Sep 17 00:00:00 2001 From: Andrea Odetti Date: Thu, 10 Mar 2022 15:39:50 +0000 Subject: [PATCH] Uthernet II: correctly initialise all default register values. Signed-off-by: Andrea Odetti --- source/Uthernet2.cpp | 17 ++++++++++++++--- source/W5100.h | 8 ++++++++ 2 files changed, 22 insertions(+), 3 deletions(-) diff --git a/source/Uthernet2.cpp b/source/Uthernet2.cpp index 74b32aec..d2adea31 100644 --- a/source/Uthernet2.cpp +++ b/source/Uthernet2.cpp @@ -1084,14 +1084,25 @@ void Uthernet2::Reset(const bool powerCycle) { resetRXTXBuffers(i); mySockets[i].clearFD(); - mySockets[i].registerAddress = static_cast(W5100_S0_BASE + (i << 8)); + const uint16_t registerAddress = static_cast(W5100_S0_BASE + (i << 8)); + mySockets[i].registerAddress = registerAddress; + + myMemory[registerAddress + W5100_SN_DHAR0] = 0xFF; + myMemory[registerAddress + W5100_SN_DHAR1] = 0xFF; + myMemory[registerAddress + W5100_SN_DHAR2] = 0xFF; + myMemory[registerAddress + W5100_SN_DHAR3] = 0xFF; + myMemory[registerAddress + W5100_SN_DHAR4] = 0xFF; + myMemory[registerAddress + W5100_SN_DHAR5] = 0xFF; + myMemory[registerAddress + W5100_SN_TTL] = 0x80; } // initial values - myMemory[W5100_RTR0] = 0x07; - myMemory[W5100_RTR1] = 0xD0; + myMemory[W5100_RTR0] = 0x07; + myMemory[W5100_RTR1] = 0xD0; + myMemory[W5100_RCR] = 0x08; setRXSizes(W5100_RMSR, 0x55); setTXSizes(W5100_TMSR, 0x55); + myMemory[W5100_PTIMER] = 0x28; } BYTE Uthernet2::IO_C0(WORD programcounter, WORD address, BYTE write, BYTE value, ULONG nCycles) diff --git a/source/W5100.h b/source/W5100.h index c9f35ec0..c07a8502 100644 --- a/source/W5100.h +++ b/source/W5100.h @@ -20,8 +20,10 @@ #define W5100_SIPR3 0x0012 #define W5100_RTR0 0x0017 #define W5100_RTR1 0x0018 +#define W5100_RCR 0x0019 #define W5100_RMSR 0x001A #define W5100_TMSR 0x001B +#define W5100_PTIMER 0x0028 #define W5100_UPORT1 0x002F #define W5100_S0_BASE 0x0400 #define W5100_S3_MAX 0x07FF @@ -58,6 +60,12 @@ #define W5100_SN_SR 0x03 #define W5100_SN_PORT0 0x04 #define W5100_SN_PORT1 0x05 +#define W5100_SN_DHAR0 0x06 +#define W5100_SN_DHAR1 0x07 +#define W5100_SN_DHAR2 0x08 +#define W5100_SN_DHAR3 0x09 +#define W5100_SN_DHAR4 0x0A +#define W5100_SN_DHAR5 0x0B #define W5100_SN_DIPR0 0x0C #define W5100_SN_DIPR1 0x0D #define W5100_SN_DIPR2 0x0E