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6522: account for underflowed cycles to ensure consistent interrupt period (#651)

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tomcw 2019-06-01 12:21:00 +01:00
parent f8bd94ae87
commit 941ef46e9a
1 changed files with 18 additions and 3 deletions
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21
source/Mockingboard.cpp
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@ -1797,11 +1797,19 @@ void MB_UpdateCycles(ULONG uExecutedCycles)
{
// Free-running mode
// - Ultima4/5 change ACCESS_TIMER1 after a couple of IRQs into tune
pMB->sy6522.TIMER1_COUNTER.w = pMB->sy6522.TIMER1_LATCH.w;
pMB->sy6522.TIMER1_COUNTER.w += pMB->sy6522.TIMER1_LATCH.w; // GH#651: account for underflowed cycles too
if (pMB->sy6522.TIMER1_COUNTER.w > pMB->sy6522.TIMER1_LATCH.w)
{
if (pMB->sy6522.TIMER1_LATCH.w)
pMB->sy6522.TIMER1_COUNTER.w %= pMB->sy6522.TIMER1_LATCH.w; // Only occurs if LATCH.w<0x0007 (# cycles for longest opcode)
else
pMB->sy6522.TIMER1_COUNTER.w = 0;
}
StartTimer1(pMB);
}
}
else if (pMB->bTimer2Active && bTimer2Underflow)
if (pMB->bTimer2Active && bTimer2Underflow)
{
UpdateIFR(pMB, 0, IxR_TIMER2);
@ -1811,7 +1819,14 @@ void MB_UpdateCycles(ULONG uExecutedCycles)
}
else
{
pMB->sy6522.TIMER2_COUNTER.w = pMB->sy6522.TIMER2_LATCH.w;
pMB->sy6522.TIMER2_COUNTER.w += pMB->sy6522.TIMER2_LATCH.w;
if (pMB->sy6522.TIMER2_COUNTER.w > pMB->sy6522.TIMER2_LATCH.w)
{
if (pMB->sy6522.TIMER2_LATCH.w)
pMB->sy6522.TIMER2_COUNTER.w %= pMB->sy6522.TIMER2_LATCH.w;
else
pMB->sy6522.TIMER2_COUNTER.w = 0;
}
StartTimer2(pMB);
}
}