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CPU: Fixed issues with OR/EOR/AND and stack addressing mode

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This commit is contained in:
Sour 2019-02-14 00:48:16 -05:00
parent 930f504861
commit 0f64559882
3 changed files with 32 additions and 19 deletions
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22
Core/Cpu.Instructions.cpp
View file

@ -459,17 +459,29 @@ Bitwise operations
*******************/ *******************/
void Cpu::AND() void Cpu::AND()
{ {
SetRegister(_state.A, _state.A & GetByteValue(), CheckFlag(ProcFlags::MemoryMode8)); if(CheckFlag(ProcFlags::MemoryMode8)) {
SetRegister(_state.A, _state.A & GetByteValue(), true);
} else {
SetRegister(_state.A, _state.A & GetWordValue(), false);
}
} }
void Cpu::EOR() void Cpu::EOR()
{ {
SetRegister(_state.A, _state.A ^ GetByteValue(), CheckFlag(ProcFlags::MemoryMode8)); if(CheckFlag(ProcFlags::MemoryMode8)) {
SetRegister(_state.A, _state.A ^ GetByteValue(), true);
} else {
SetRegister(_state.A, _state.A ^ GetWordValue(), false);
}
} }
void Cpu::ORA() void Cpu::ORA()
{ {
SetRegister(_state.A, _state.A | GetByteValue(), CheckFlag(ProcFlags::MemoryMode8)); if(CheckFlag(ProcFlags::MemoryMode8)) {
SetRegister(_state.A, _state.A | GetByteValue(), true);
} else {
SetRegister(_state.A, _state.A | GetWordValue(), false);
}
} }
/**************** /****************
@ -840,7 +852,7 @@ void Cpu::TCD()
void Cpu::TCS() void Cpu::TCS()
{ {
_state.SP = _state.A; SetSP(_state.A);
} }
void Cpu::TDC() void Cpu::TDC()
@ -865,7 +877,7 @@ void Cpu::TXA()
void Cpu::TXS() void Cpu::TXS()
{ {
_state.SP = _state.X; SetSP(_state.X);
} }
void Cpu::TXY() void Cpu::TXY()

27
Core/Cpu.cpp
View file

@ -198,23 +198,13 @@ uint16_t Cpu::GetWordValue()
void Cpu::PushByte(uint8_t value) void Cpu::PushByte(uint8_t value)
{ {
if(_state.EmulationMode) { Write(_state.SP, value);
_state.SP = 0x100 | (_state.SP & 0xFF); SetSP(_state.SP - 1);
Write(_state.SP, value);
_state.SP = 0x100 | ((_state.SP - 1) & 0xFF);
} else {
Write(_state.SP, value);
_state.SP--;
}
} }
uint8_t Cpu::PopByte() uint8_t Cpu::PopByte()
{ {
if(_state.EmulationMode) { SetSP(_state.SP + 1);
_state.SP = 0x100 | ((_state.SP + 1) & 0xFF);
} else {
_state.SP++;
}
return ReadData(_state.SP); return ReadData(_state.SP);
} }
@ -299,13 +289,22 @@ uint32_t Cpu::FetchEffectiveAddress()
case AddrMode::StkRelIndIdxY: { case AddrMode::StkRelIndIdxY: {
uint16_t addr = (uint16_t)(ReadOperandByte() + _state.SP); uint16_t addr = (uint16_t)(ReadOperandByte() + _state.SP);
return (GetDataAddress(addr) + _state.Y) & 0xFFFFFF; return (GetDataAddress(ReadDataWord(addr)) + _state.Y) & 0xFFFFFF;
} }
} }
throw new std::runtime_error("Unreacheable code"); throw new std::runtime_error("Unreacheable code");
} }
void Cpu::SetSP(uint16_t sp)
{
if(_state.EmulationMode) {
_state.SP = 0x100 | (sp & 0xFF);
} else {
_state.SP = sp;
}
}
void Cpu::SetRegister(uint8_t &reg, uint8_t value) void Cpu::SetRegister(uint8_t &reg, uint8_t value)
{ {
SetZeroNegativeFlags(value); SetZeroNegativeFlags(value);

2
Core/Cpu.h
View file

@ -52,6 +52,8 @@ private:
uint32_t ReadOperandLong(); uint32_t ReadOperandLong();
uint32_t FetchEffectiveAddress(); uint32_t FetchEffectiveAddress();
void SetSP(uint16_t sp);
void SetRegister(uint8_t &reg, uint8_t value); void SetRegister(uint8_t &reg, uint8_t value);
void SetRegister(uint16_t &reg, uint16_t value, bool eightBitMode); void SetRegister(uint16_t &reg, uint16_t value, bool eightBitMode);