From 53de61ba90cb55b64df5f93d9bf4153659e281b8 Mon Sep 17 00:00:00 2001
From: Sour <mesenemu@gmail.com>
Date: Tue, 26 Mar 2019 19:07:06 -0400
Subject: [PATCH] HDMA: Fixed timings on HDMA initalization (and fixed
 regression that caused DRAM refresh to not longer occur)

---
 Core/DmaController.cpp |  6 +++---
 Core/Ppu.cpp           | 22 ++++++++++------------
 2 files changed, 13 insertions(+), 15 deletions(-)

diff --git a/Core/DmaController.cpp b/Core/DmaController.cpp
index d8233a6..9517218 100644
--- a/Core/DmaController.cpp
+++ b/Core/DmaController.cpp
@@ -114,10 +114,10 @@ void DmaController::InitHdmaChannels()
 				ch.TransferSize = (msb << 8) | lsb;
 
 				//"and 24 master cycles for each channel set for indirect HDMA"
-				_memoryManager->IncrementMasterClockValue<24>();
+				_memoryManager->IncrementMasterClockValue<16>();
 			} else {
 				//"plus 8 master cycles for each channel set for direct HDMA"
-				_memoryManager->IncrementMasterClockValue<8>();
+				_memoryManager->IncrementMasterClockValue<4>();
 			}
 			
 			//4. Set DoTransfer to true.
@@ -216,7 +216,7 @@ void DmaController::ProcessHdmaChannels()
 					}
 
 					//"If a new indirect address is required, 16 master cycles are taken to load it."
-					_memoryManager->IncrementMasterClockValue<8>(); //minus 8 before the ReadDmas call will increment it by 4 twice
+					_memoryManager->IncrementMasterClockValue<8>(); //minus 8 because the ReadDmas call will increment it by 4 twice
 				}
 
 				//"c. If $43xA is zero, terminate this HDMA channel for this frame. The bit in $420c is not cleared, though, so it may be automatically restarted next frame."
diff --git a/Core/Ppu.cpp b/Core/Ppu.cpp
index c68b775..efccd16 100644
--- a/Core/Ppu.cpp
+++ b/Core/Ppu.cpp
@@ -164,19 +164,17 @@ void Ppu::Exec()
 		}
 	}
 	
-	if(_scanline <= (_overscanMode ? 239 : 224)) {
-		if(_cycle == 278) {
-			if(_scanline != 0) {
-				RenderScanline();
-			}
-			if(!_forcedVblank) {
-				EvaluateNextLineSprites();
-				_console->GetDmaController()->ProcessHdmaChannels();
-			}
-		} else if(_scanline == 0 && _cycle == 6) {
-			//TODO : To verify: Do HDMA channels get initialized even in forced blank?
-			_console->GetDmaController()->InitHdmaChannels();
+	if(_cycle == 278 && _scanline <= (_overscanMode ? 239 : 224)) {
+		if(_scanline != 0) {
+			RenderScanline();
 		}
+		if(!_forcedVblank) {
+			EvaluateNextLineSprites();
+			_console->GetDmaController()->ProcessHdmaChannels();
+		}
+	} else if(_scanline == 0 && _cycle == 6) {
+		//TODO : To verify: Do HDMA channels get initialized even in forced blank?
+		_console->GetDmaController()->InitHdmaChannels();
 	} else if((_cycle == 134 || _cycle == 135) && (_console->GetMemoryManager()->GetMasterClock() & 0x07) == 0) {
 		//TODO Approximation (DRAM refresh timing is not exact)
 		_console->GetMemoryManager()->IncrementMasterClockValue<40>();