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SA-1: Fixed timing regressions

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Memory handlers did not have the _memoryType value set, which caused some memory accesses to be much faster than expected
This commit is contained in:
Sour 2020-03-01 18:24:33 -05:00
parent 1d6253d2e5
commit 6539b92502
21 changed files with 28 additions and 29 deletions
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2
Core/BaseCoprocessor.h
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@ -6,6 +6,8 @@
class BaseCoprocessor : public ISerializable, public IMemoryHandler
{
public:
using IMemoryHandler::IMemoryHandler;
virtual void Reset() = 0;
virtual void ProcessEndOfFrame() { }

2
Core/BsxCart.cpp
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@ -9,7 +9,7 @@
#include "RamHandler.h"
#include "EmuSettings.h"
BsxCart::BsxCart(Console* console, BsxMemoryPack* memPack)
BsxCart::BsxCart(Console* console, BsxMemoryPack* memPack) : BaseCoprocessor(SnesMemoryType::Register)
{
_console = console;
_memoryManager = _console->GetMemoryManager().get();

2
Core/BsxSatellaview.cpp
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@ -5,7 +5,7 @@
#include "EmuSettings.h"
#include "../Utilities/Serializer.h"
BsxSatellaview::BsxSatellaview(Console* console, IMemoryHandler* bBusHandler)
BsxSatellaview::BsxSatellaview(Console* console, IMemoryHandler* bBusHandler) : IMemoryHandler(SnesMemoryType::Register)
{
_console = console;
_memoryManager = console->GetMemoryManager().get();

2
Core/CpuBwRamHandler.h
View file

@ -15,7 +15,7 @@ private:
Sa1* _sa1;
public:
CpuBwRamHandler(IMemoryHandler* handler, Sa1State* state, Sa1* sa1)
CpuBwRamHandler(IMemoryHandler* handler, Sa1State* state, Sa1* sa1) : IMemoryHandler(handler->GetMemoryType())
{
_handler = handler;
_sa1 = sa1;

2
Core/Cx4.cpp
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@ -13,7 +13,7 @@
//TODO: CPU shouldn't have access to PRG ROM while the CX4 is loading from PRG ROM
//TODO: Timings are apparently not perfect (desync in MMX2 intro)
Cx4::Cx4(Console* console)
Cx4::Cx4(Console* console) : BaseCoprocessor(SnesMemoryType::Register)
{
_console = console;
_memoryType = SnesMemoryType::Register;

2
Core/Gsu.cpp
View file

@ -12,7 +12,7 @@
#include "BatteryManager.h"
#include "../Utilities/HexUtilities.h"
Gsu::Gsu(Console *console, uint32_t gsuRamSize)
Gsu::Gsu(Console *console, uint32_t gsuRamSize) : BaseCoprocessor(SnesMemoryType::Register)
{
_console = console;
_memoryManager = console->GetMemoryManager().get();

3
Core/GsuRamHandler.h
View file

@ -10,9 +10,8 @@ private:
IMemoryHandler *_handler;
public:
GsuRamHandler(GsuState &state, IMemoryHandler *handler)
GsuRamHandler(GsuState &state, IMemoryHandler *handler) : IMemoryHandler(SnesMemoryType::GsuWorkRam)
{
_memoryType = SnesMemoryType::GsuWorkRam;
_handler = handler;
_state = &state;
}

3
Core/GsuRomHandler.h
View file

@ -10,9 +10,8 @@ private:
IMemoryHandler *_romHandler;
public:
GsuRomHandler(GsuState &state, IMemoryHandler *romHandler)
GsuRomHandler(GsuState &state, IMemoryHandler *romHandler) : IMemoryHandler(SnesMemoryType::PrgRom)
{
_memoryType = SnesMemoryType::PrgRom;
_romHandler = romHandler;
_state = &state;
}

12
Core/IMemoryHandler.h
View file

@ -8,6 +8,13 @@ protected:
SnesMemoryType _memoryType;
public:
IMemoryHandler(SnesMemoryType memType)
{
_memoryType = memType;
}
virtual ~IMemoryHandler() {}
virtual uint8_t Read(uint32_t addr) = 0;
virtual uint8_t Peek(uint32_t addr) = 0;
virtual void PeekBlock(uint32_t addr, uint8_t *output) = 0;
@ -19,9 +26,4 @@ public:
}
virtual AddressInfo GetAbsoluteAddress(uint32_t address) = 0;
//virtual void GetMemoryRanges(MemoryRanges &ranges) = 0;
//virtual uint8_t PeekRAM(uint16_t addr) { return 0; }
virtual ~IMemoryHandler() {}
};

2
Core/NecDsp.cpp
View file

@ -13,7 +13,7 @@
#include "FirmwareHelper.h"
#include "../Utilities/FolderUtilities.h"
NecDsp::NecDsp(CoprocessorType type, Console* console, vector<uint8_t> &programRom, vector<uint8_t> &dataRom)
NecDsp::NecDsp(CoprocessorType type, Console* console, vector<uint8_t> &programRom, vector<uint8_t> &dataRom) : BaseCoprocessor(SnesMemoryType::Register)
{
_console = console;
_type = type;

2
Core/Obc1.cpp
View file

@ -4,7 +4,7 @@
#include "MemoryManager.h"
#include "MemoryMappings.h"
Obc1::Obc1(Console* console, uint8_t* saveRam, uint32_t saveRamSize)
Obc1::Obc1(Console* console, uint8_t* saveRam, uint32_t saveRamSize) : BaseCoprocessor(SnesMemoryType::Register)
{
MemoryMappings *mappings = console->GetMemoryManager()->GetMemoryMappings();
mappings->RegisterHandler(0x00, 0x3F, 0x6000, 0x7FFF, this);

2
Core/RamHandler.h
View file

@ -13,7 +13,7 @@ protected:
uint32_t _offset;
public:
RamHandler(uint8_t *ram, uint32_t offset, uint32_t size, SnesMemoryType memoryType)
RamHandler(uint8_t *ram, uint32_t offset, uint32_t size, SnesMemoryType memoryType) : IMemoryHandler(memoryType)
{
_ram = ram + offset;
_offset = offset;

3
Core/RegisterHandlerA.h
View file

@ -13,12 +13,11 @@ private:
ControlManager *_controlManager;
public:
RegisterHandlerA(DmaController *dmaController, InternalRegisters *regs, ControlManager *controlManager)
RegisterHandlerA(DmaController *dmaController, InternalRegisters *regs, ControlManager *controlManager) : IMemoryHandler(SnesMemoryType::Register)
{
_regs = regs;
_dmaController = dmaController;
_controlManager = controlManager;
_memoryType = SnesMemoryType::Register;
}
uint8_t Read(uint32_t addr) override

3
Core/RegisterHandlerB.cpp
View file

@ -9,7 +9,7 @@
#include "CheatManager.h"
#include "../Utilities/Serializer.h"
RegisterHandlerB::RegisterHandlerB(Console *console, Ppu * ppu, Spc * spc, uint8_t * workRam)
RegisterHandlerB::RegisterHandlerB(Console *console, Ppu * ppu, Spc * spc, uint8_t * workRam) : IMemoryHandler(SnesMemoryType::Register)
{
_console = console;
_cheatManager = console->GetCheatManager().get();
@ -19,7 +19,6 @@ RegisterHandlerB::RegisterHandlerB(Console *console, Ppu * ppu, Spc * spc, uint8
_msu1 = console->GetMsu1().get();
_workRam = workRam;
_wramPosition = 0;
_memoryType = SnesMemoryType::Register;
}
uint8_t RegisterHandlerB::Read(uint32_t addr)

2
Core/Sa1.cpp
View file

@ -15,7 +15,7 @@
#include "MessageManager.h"
#include "../Utilities/HexUtilities.h"
Sa1::Sa1(Console* console)
Sa1::Sa1(Console* console) : BaseCoprocessor(SnesMemoryType::Register)
{
_console = console;
_memoryManager = console->GetMemoryManager().get();

2
Core/Sa1BwRamHandler.h
View file

@ -37,7 +37,7 @@ private:
}
public:
Sa1BwRamHandler(uint8_t* bwRam, uint32_t bwRamSize, Sa1State* state)
Sa1BwRamHandler(uint8_t* bwRam, uint32_t bwRamSize, Sa1State* state) : IMemoryHandler(SnesMemoryType::SaveRam)
{
_ram = bwRam;
_mask = bwRamSize - 1;

3
Core/Sa1IRamHandler.h
View file

@ -18,10 +18,9 @@ private:
}
public:
Sa1IRamHandler(uint8_t *ram)
Sa1IRamHandler(uint8_t *ram) : IMemoryHandler(SnesMemoryType::Sa1InternalRam)
{
_ram = ram;
_memoryType = SnesMemoryType::Sa1InternalRam;
}
uint8_t Read(uint32_t addr) override

2
Core/Sa1VectorHandler.h
View file

@ -11,7 +11,7 @@ private:
Sa1State* _state;
public:
Sa1VectorHandler(IMemoryHandler* handler, Sa1State* state)
Sa1VectorHandler(IMemoryHandler* handler, Sa1State* state) : IMemoryHandler(handler->GetMemoryType())
{
_handler = handler;
_state = state;

2
Core/Sdd1.cpp
View file

@ -6,7 +6,7 @@
#include "MemoryManager.h"
#include "MemoryMappings.h"
Sdd1::Sdd1(Console* console)
Sdd1::Sdd1(Console* console) : BaseCoprocessor(SnesMemoryType::Register)
{
//This handler is used to dynamically map the ROM based on the banking registers
_sdd1Mmc.reset(new Sdd1Mmc(_state, console->GetCartridge().get()));

2
Core/Sdd1Mmc.cpp
View file

@ -3,7 +3,7 @@
#include "Sdd1Types.h"
#include "BaseCartridge.h"
Sdd1Mmc::Sdd1Mmc(Sdd1State &state, BaseCartridge *cart)
Sdd1Mmc::Sdd1Mmc(Sdd1State &state, BaseCartridge *cart) : IMemoryHandler(SnesMemoryType::Register)
{
_romHandlers = &cart->GetPrgRomHandlers();
_handlerMask = (uint32_t)((*_romHandlers).size() - 1);

2
Core/Spc7110.cpp
View file

@ -10,7 +10,7 @@
#include "MessageManager.h"
#include "../Utilities/HexUtilities.h"
Spc7110::Spc7110(Console* console, bool useRtc)
Spc7110::Spc7110(Console* console, bool useRtc) : BaseCoprocessor(SnesMemoryType::Register)
{
_console = console;
_cart = console->GetCartridge().get();