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HDMA: Improved HDMA init timing (and fixed potential problems caused by running it in the middle of a PPU cycle)

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This commit is contained in:
Sour 2019-03-25 22:59:18 -04:00
parent e0b0ac3a96
commit 713b83c1fb
1 changed files with 12 additions and 8 deletions
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20
Core/Ppu.cpp
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@ -140,7 +140,6 @@ void Ppu::Exec()
if(_mosaicEnabled) { if(_mosaicEnabled) {
_mosaicStartScanline = 0; _mosaicStartScanline = 0;
} }
_console->GetDmaController()->InitHdmaChannels();
} }
if(_regs->IsVerticalIrqEnabled() && !_regs->IsHorizontalIrqEnabled() && _scanline == _regs->GetVerticalTimer()) { if(_regs->IsVerticalIrqEnabled() && !_regs->IsHorizontalIrqEnabled() && _scanline == _regs->GetVerticalTimer()) {
@ -165,13 +164,18 @@ void Ppu::Exec()
} }
} }
if(_cycle == 278 && _scanline <= (_overscanMode ? 239 : 224)) { if(_scanline <= (_overscanMode ? 239 : 224)) {
if(_scanline != 0) { if(_cycle == 278) {
RenderScanline(); if(_scanline != 0) {
} RenderScanline();
if(!_forcedVblank) { }
EvaluateNextLineSprites(); if(!_forcedVblank) {
_console->GetDmaController()->ProcessHdmaChannels(); EvaluateNextLineSprites();
_console->GetDmaController()->ProcessHdmaChannels();
}
} else if(_scanline == 0 && _cycle == 6) {
//TODO : To verify: Do HDMA channels get initialized even in forced blank?
_console->GetDmaController()->InitHdmaChannels();
} }
} else if((_cycle == 134 || _cycle == 135) && (_console->GetMemoryManager()->GetMasterClock() & 0x07) == 0) { } else if((_cycle == 134 || _cycle == 135) && (_console->GetMemoryManager()->GetMasterClock() & 0x07) == 0) {
//TODO Approximation (DRAM refresh timing is not exact) //TODO Approximation (DRAM refresh timing is not exact)