HDMA: Set DoTransfer flag to true for all 8 HDMA channels during init if at least 1 HDMA channel is active (Fixed "Ladida_lol" test)
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Sour
parent
9d90fb9e52
commit
7bb0910607
1 changed files with 97 additions and 81 deletions
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@ -98,17 +98,25 @@ void DmaController::RunDma(DmaChannelConfig &channel)
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void DmaController::InitHdmaChannels()
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{
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if(_hdmaChannels) {
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//"The overhead is ~18 master cycles"
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_memoryManager->IncrementMasterClockValue<18>();
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for(int i = 0; i < 8; i++) {
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//Reset internal flags on every frame, whether or not the channels are enabled
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_channel[i].HdmaFinished = false;
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_channel[i].DoTransfer = false; //not resetting this causes graphical glitches in some games (Aladdin, Super Ghouls and Ghosts)
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}
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if(!_hdmaChannels) {
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//No channels are enabled, no more processing needs to be done
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return;
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}
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//"The overhead is ~18 master cycles"
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_memoryManager->IncrementMasterClockValue<18>();
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for(int i = 0; i < 8; i++) {
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DmaChannelConfig &ch = _channel[i];
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//Reset internal flags on every frame
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ch.HdmaFinished = false;
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ch.DoTransfer = false; //not resetting this causes graphical glitches in some games (Aladdin, Super Ghouls and Ghosts)
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//Set DoTransfer to true for all channels if any HDMA channel is enabled
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ch.DoTransfer = true;
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if(_hdmaChannels & (1 << i)) {
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//"1. Copy AAddress into Address."
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@ -134,9 +142,6 @@ void DmaController::InitHdmaChannels()
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//"plus 8 master cycles for each channel set for direct HDMA"
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_memoryManager->IncrementMasterClockValue<4>();
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}
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//4. Set DoTransfer to true.
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ch.DoTransfer = true;
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}
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}
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}
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@ -175,78 +180,89 @@ void DmaController::RunHdmaTransfer(DmaChannelConfig &channel)
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void DmaController::ProcessHdmaChannels()
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{
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bool needOverhead = true;
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if(_hdmaChannels) {
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_hdmaPending = true;
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for(int i = 0; i < 8; i++) {
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if(_hdmaChannels & (1 << i)) {
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_channel[i].InterruptedByHdma = true;
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}
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}
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for(int i = 0; i < 8; i++) {
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DmaChannelConfig &ch = _channel[i];
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if((_hdmaChannels & (1 << i)) == 0 || ch.HdmaFinished) {
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continue;
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}
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if(needOverhead) {
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//"For each scanline during which HDMA is active (i.e.at least one channel has not yet terminated for the frame), there are ~18 master cycles overhead."
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_memoryManager->IncrementMasterClockValue<8>();
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needOverhead = false;
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}
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//"Each active channel incurs another 8 master cycles overhead for every scanline"
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_memoryManager->IncrementMasterClockValue<8>();
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//1. If DoTransfer is false, skip to step 3.
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if(ch.DoTransfer) {
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//2. For the number of bytes (1, 2, or 4) required for this Transfer Mode...
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RunHdmaTransfer(ch);
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}
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//3. Decrement $43xA.
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ch.HdmaLineCounterAndRepeat--;
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//4. Set DoTransfer to the value of Repeat.
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ch.DoTransfer = (ch.HdmaLineCounterAndRepeat & 0x80) != 0;
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//5. If Line Counter is zero...
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if((ch.HdmaLineCounterAndRepeat & 0x7F) == 0) {
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//"a. Read the next byte from Address into $43xA (thus, into both Line Counter and Repeat)."
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ch.HdmaLineCounterAndRepeat = _memoryManager->ReadDma((ch.SrcBank << 16) | ch.HdmaTableAddress++, true);
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//"b. If Addressing Mode is Indirect, read two bytes from Address into Indirect Address(and increment Address by two bytes)."
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if(ch.HdmaIndirectAddressing) {
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if(ch.HdmaLineCounterAndRepeat == 0) {
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//"One oddity: if $43xA is 0 and this is the last active HDMA channel for this scanline, only load one byte for Address,
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//and use the $00 for the low byte.So Address ends up incremented one less than otherwise expected, and one less CPU Cycle is used."
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uint8_t msb = _memoryManager->ReadDma((ch.SrcBank << 16) | ch.HdmaTableAddress++, true);
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ch.TransferSize = (msb << 8);
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} else {
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uint8_t lsb = _memoryManager->ReadDma((ch.SrcBank << 16) | ch.HdmaTableAddress++, true);
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uint8_t msb = _memoryManager->ReadDma((ch.SrcBank << 16) | ch.HdmaTableAddress++, true);
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ch.TransferSize = (msb << 8) | lsb;
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}
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//"If a new indirect address is required, 16 master cycles are taken to load it."
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_memoryManager->IncrementMasterClockValue<8>(); //minus 8 because the ReadDmas call will increment it by 4 twice
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}
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//"c. If $43xA is zero, terminate this HDMA channel for this frame. The bit in $420c is not cleared, though, so it may be automatically restarted next frame."
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if(ch.HdmaLineCounterAndRepeat == 0) {
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ch.HdmaFinished = true;
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}
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//"d. Set DoTransfer to true."
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ch.DoTransfer = true;
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}
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}
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//When DMA runs, the next instruction will not check the NMI/IRQ flags, which allows 2 instructions to run after DMA
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_nmiIrqDelayCounter = 2;
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if(!_hdmaChannels) {
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return;
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}
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_hdmaPending = true;
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for(int i = 0; i < 8; i++) {
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if(_hdmaChannels & (1 << i)) {
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_channel[i].InterruptedByHdma = true;
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}
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}
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//Run all the DMA transfers for each channel first, before fetching data for the next scanline
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bool needOverhead = true;
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for(int i = 0; i < 8; i++) {
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DmaChannelConfig &ch = _channel[i];
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if((_hdmaChannels & (1 << i)) == 0 || ch.HdmaFinished) {
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continue;
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}
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if(needOverhead) {
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//"For each scanline during which HDMA is active (i.e.at least one channel has not yet terminated for the frame), there are ~18 master cycles overhead."
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_memoryManager->IncrementMasterClockValue<8>();
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needOverhead = false;
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}
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//"Each active channel incurs another 8 master cycles overhead for every scanline"
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_memoryManager->IncrementMasterClockValue<8>();
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//1. If DoTransfer is false, skip to step 3.
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if(ch.DoTransfer) {
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//2. For the number of bytes (1, 2, or 4) required for this Transfer Mode...
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RunHdmaTransfer(ch);
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}
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}
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//Update the channel's state & fetch data for the next scanline
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for(int i = 0; i < 8; i++) {
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DmaChannelConfig &ch = _channel[i];
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if((_hdmaChannels & (1 << i)) == 0 || ch.HdmaFinished) {
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continue;
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}
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//3. Decrement $43xA.
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ch.HdmaLineCounterAndRepeat--;
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//4. Set DoTransfer to the value of Repeat.
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ch.DoTransfer = (ch.HdmaLineCounterAndRepeat & 0x80) != 0;
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//5. If Line Counter is zero...
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if((ch.HdmaLineCounterAndRepeat & 0x7F) == 0) {
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//"a. Read the next byte from Address into $43xA (thus, into both Line Counter and Repeat)."
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ch.HdmaLineCounterAndRepeat = _memoryManager->ReadDma((ch.SrcBank << 16) | ch.HdmaTableAddress++, true);
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//"b. If Addressing Mode is Indirect, read two bytes from Address into Indirect Address(and increment Address by two bytes)."
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if(ch.HdmaIndirectAddressing) {
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if(ch.HdmaLineCounterAndRepeat == 0) {
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//"One oddity: if $43xA is 0 and this is the last active HDMA channel for this scanline, only load one byte for Address,
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//and use the $00 for the low byte.So Address ends up incremented one less than otherwise expected, and one less CPU Cycle is used."
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uint8_t msb = _memoryManager->ReadDma((ch.SrcBank << 16) | ch.HdmaTableAddress++, true);
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ch.TransferSize = (msb << 8);
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} else {
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uint8_t lsb = _memoryManager->ReadDma((ch.SrcBank << 16) | ch.HdmaTableAddress++, true);
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uint8_t msb = _memoryManager->ReadDma((ch.SrcBank << 16) | ch.HdmaTableAddress++, true);
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ch.TransferSize = (msb << 8) | lsb;
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}
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//"If a new indirect address is required, 16 master cycles are taken to load it."
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_memoryManager->IncrementMasterClockValue<8>(); //minus 8 because the ReadDmas call will increment it by 4 twice
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}
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//"c. If $43xA is zero, terminate this HDMA channel for this frame. The bit in $420c is not cleared, though, so it may be automatically restarted next frame."
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if(ch.HdmaLineCounterAndRepeat == 0) {
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ch.HdmaFinished = true;
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}
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//"d. Set DoTransfer to true."
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ch.DoTransfer = true;
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}
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}
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//When DMA runs, the next instruction will not check the NMI/IRQ flags, which allows 2 instructions to run after DMA
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_nmiIrqDelayCounter = 2;
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}
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void DmaController::Write(uint16_t addr, uint8_t value)
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