Debugger: Added SA-1 tab to register viewer
This commit is contained in:
Sour
parent
455f705e45
commit
7c79bf2974
11 changed files with 313 additions and 25 deletions
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@ -6,6 +6,7 @@
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#include "NecDspTypes.h"
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#include "GsuTypes.h"
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#include "Cx4Types.h"
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#include "Sa1Types.h"
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#include "InternalRegisterTypes.h"
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#include "DmaControllerTypes.h"
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@ -17,7 +18,7 @@ struct DebugState
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SpcState Spc;
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DspState Dsp;
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NecDspState NecDsp;
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CpuState Sa1;
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DebugSa1State Sa1;
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GsuState Gsu;
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Cx4State Cx4;
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@ -424,7 +424,7 @@ void Debugger::GetState(DebugState &state, bool partialPpuState)
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state.NecDsp = _cart->GetDsp()->GetState();
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}
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if(_cart->GetSa1()) {
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state.Sa1 = _cart->GetSa1()->GetCpuState();
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state.Sa1 = _cart->GetSa1()->GetState();
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}
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if(_cart->GetGsu()) {
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state.Gsu = _cart->GetGsu()->GetState();
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@ -778,6 +778,14 @@ uint32_t Sa1::DebugGetInternalRamSize()
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return Sa1::InternalRamSize;
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}
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DebugSa1State Sa1::GetState()
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{
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return {
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_cpu->GetState(),
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_state
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};
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}
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CpuState Sa1::GetCpuState()
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{
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return _cpu->GetState();
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@ -88,7 +88,9 @@ public:
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uint8_t* DebugGetInternalRam();
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uint32_t DebugGetInternalRamSize();
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DebugSa1State GetState();
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CpuState GetCpuState();
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uint16_t ReadVector(uint16_t vector);
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MemoryMappings* GetMemoryMappings();
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};
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@ -1,5 +1,6 @@
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#pragma once
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#include "stdafx.h"
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#include "CpuTypes.h"
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enum class Sa1MathOp
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{
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@ -106,3 +107,9 @@ struct Sa1State
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uint8_t Banks[4];
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};
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struct DebugSa1State
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{
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CpuState Cpu;
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Sa1State Sa1;
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};
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@ -492,7 +492,7 @@ void TraceLogger::GetTraceRow(string &output, CpuType cpuType, DisassemblyInfo &
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case CpuType::Cpu: GetTraceRow(output, state.Cpu, state.Ppu, disassemblyInfo, SnesMemoryType::CpuMemory, cpuType); break;
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case CpuType::Spc: GetTraceRow(output, state.Spc, state.Ppu, disassemblyInfo); break;
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case CpuType::NecDsp: GetTraceRow(output, state.NecDsp, state.Ppu, disassemblyInfo); break;
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case CpuType::Sa1: GetTraceRow(output, state.Sa1, state.Ppu, disassemblyInfo, SnesMemoryType::Sa1Memory, cpuType); break;
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case CpuType::Sa1: GetTraceRow(output, state.Sa1.Cpu, state.Ppu, disassemblyInfo, SnesMemoryType::Sa1Memory, cpuType); break;
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case CpuType::Gsu: GetTraceRow(output, state.Gsu, state.Ppu, disassemblyInfo); break;
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case CpuType::Cx4: GetTraceRow(output, state.Cx4, state.Ppu, disassemblyInfo); break;
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}
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@ -588,7 +588,7 @@ const char* TraceLogger::GetExecutionTrace(uint32_t lineCount)
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case CpuType::Cpu: _executionTrace += "\x2\x1" + HexUtilities::ToHex24((state.Cpu.K << 16) | state.Cpu.PC) + "\x1"; break;
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case CpuType::Spc: _executionTrace += "\x3\x1" + HexUtilities::ToHex(state.Spc.PC) + "\x1"; break;
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case CpuType::NecDsp: _executionTrace += "\x4\x1" + HexUtilities::ToHex(state.NecDsp.PC) + "\x1"; break;
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case CpuType::Sa1: _executionTrace += "\x4\x1" + HexUtilities::ToHex24((state.Sa1.K << 16) | state.Sa1.PC) + "\x1"; break;
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case CpuType::Sa1: _executionTrace += "\x4\x1" + HexUtilities::ToHex24((state.Sa1.Cpu.K << 16) | state.Sa1.Cpu.PC) + "\x1"; break;
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case CpuType::Gsu: _executionTrace += "\x4\x1" + HexUtilities::ToHex24((state.Gsu.ProgramBank << 16) | state.Gsu.R[15]) + "\x1"; break;
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case CpuType::Cx4: _executionTrace += "\x4\x1" + HexUtilities::ToHex24((state.Cx4.Cache.Address[state.Cx4.Cache.Page] + (state.Cx4.PC * 2)) & 0xFFFFFF) + "\x1"; break;
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}
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@ -21,7 +21,7 @@ namespace Mesen.GUI.Debugger.Code
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protected override int GetFullAddress(int address, int length)
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{
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CpuState state = DebugApi.GetState().Sa1;
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CpuState state = DebugApi.GetState().Sa1.Cpu;
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if(length == 4) {
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//Append current DB register to 2-byte addresses
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return (state.DBR << 16) | address;
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@ -42,7 +42,7 @@ namespace Mesen.GUI.Debugger.Controls
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switch(_cpuType) {
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case CpuType.Cpu: _programCounter = (uint)(state.Cpu.K << 16) | state.Cpu.PC; break;
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case CpuType.Sa1: _programCounter = (uint)(state.Sa1.K << 16) | state.Sa1.PC; break;
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case CpuType.Sa1: _programCounter = (uint)(state.Sa1.Cpu.K << 16) | state.Sa1.Cpu.PC; break;
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case CpuType.Spc: _programCounter = (uint)state.Spc.PC; break;
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default: throw new Exception("Invalid cpu type");
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}
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@ -26,6 +26,10 @@ namespace Mesen.GUI.Debugger
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private byte _reg4211;
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private byte _reg4212;
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private CoprocessorType _coprocessorType;
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private TabPage tpgCoprocessor;
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private ctrlPropertyList ctrlCoprocessor;
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public ctrlScanlineCycleSelect ScanlineCycleSelect { get { return this.ctrlScanlineCycleSelect; } }
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public frmRegisterViewer()
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@ -55,6 +59,8 @@ namespace Mesen.GUI.Debugger
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_refreshManager.AutoRefresh = config.AutoRefresh;
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_refreshManager.AutoRefreshSpeed = RefreshSpeed.High;
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UpdateTabs();
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RefreshData();
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RefreshViewer();
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@ -82,9 +88,30 @@ namespace Mesen.GUI.Debugger
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base.OnFormClosed(e);
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}
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private void UpdateTabs()
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{
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if(tpgCoprocessor != null) {
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tabMain.TabPages.Remove(tpgCoprocessor);
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}
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_coprocessorType = EmuApi.GetRomInfo().CoprocessorType;
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if(_coprocessorType == CoprocessorType.SA1) {
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tpgCoprocessor = new TabPage();
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tpgCoprocessor.Text = "SA-1";
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ctrlCoprocessor = new ctrlPropertyList();
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ctrlCoprocessor.Dock = DockStyle.Fill;
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tpgCoprocessor.Controls.Add(ctrlCoprocessor);
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tabMain.TabPages.Add(tpgCoprocessor);
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}
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}
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private void OnNotificationReceived(NotificationEventArgs e)
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{
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switch(e.NotificationType) {
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case ConsoleNotificationType.GameLoaded:
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this.BeginInvoke((Action)(() => UpdateTabs()));
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break;
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case ConsoleNotificationType.CodeBreak:
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RefreshData();
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this.BeginInvoke((Action)(() => {
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@ -149,7 +176,7 @@ namespace Mesen.GUI.Debugger
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});
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} else if(tabMain.SelectedTab == tpgDma) {
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List<RegEntry> entries = new List<RegEntry>();
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//TODO
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/*for(int i = 0; i < 8; i++) {
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entries.Add(new RegEntry("$420C." + i.ToString(), "HDMA Channel " + i.ToString() + " Enabled", _state.DmaChannels[i].DmaActive));
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@ -205,7 +232,7 @@ namespace Mesen.GUI.Debugger
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new RegEntry("$F8 - $F9", "RAM Registers", null),
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new RegEntry("$F8", "RAM Reg 0", spc.RamReg[0], Format.X8),
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new RegEntry("$F9", "RAM Reg 1", spc.RamReg[1], Format.X8),
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new RegEntry("$FA - $FF", "Timers", null),
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new RegEntry("$FA", "Timer 0 Divider", spc.Timer0.Target, Format.X8),
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new RegEntry("$FA", "Timer 0 Frequency", GetTimerFrequency(8000, spc.Timer0.Target)),
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@ -450,6 +477,134 @@ namespace Mesen.GUI.Debugger
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new RegEntry("$2133.3", "High Resolution Mode", ppu.HiResMode),
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new RegEntry("$2133.4", "Ext. BG Enabled", ppu.ExtBgEnabled),
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});
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} else if(tabMain.SelectedTab == tpgCoprocessor) {
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if(_coprocessorType == CoprocessorType.SA1) {
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Sa1State sa1 = _state.Sa1.Sa1;
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List<RegEntry> entries = new List<RegEntry>() {
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new RegEntry("$2200", "SA-1 CPU Control", null),
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new RegEntry("$2200.0-3", "Message", sa1.Sa1MessageReceived, Format.X8),
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new RegEntry("$2200.4", "NMI Requested", sa1.Sa1NmiRequested),
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new RegEntry("$2200.5", "Reset", sa1.Sa1Reset),
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new RegEntry("$2200.6", "Wait", sa1.Sa1Wait),
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new RegEntry("$2200.7", "IRQ Requested", sa1.Sa1IrqRequested),
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new RegEntry("$2201", "S-CPU Interrupt Enable", null),
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new RegEntry("$2201.5", "Character Conversion IRQ Enable", sa1.CharConvIrqEnabled),
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new RegEntry("$2201.7", "IRQ Enabled", sa1.CpuIrqEnabled),
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new RegEntry("$2202", "S-CPU Interrupt Clear", null),
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new RegEntry("$2202.5", "Character IRQ Flag", sa1.CharConvIrqFlag),
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new RegEntry("$2202.7", "IRQ Flag", sa1.CpuIrqRequested),
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new RegEntry("$2203/4", "SA-1 Reset Vector", sa1.Sa1ResetVector, Format.X16),
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new RegEntry("$2205/6", "SA-1 NMI Vector", sa1.Sa1ResetVector, Format.X16),
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new RegEntry("$2207/8", "SA-1 IRQ Vector", sa1.Sa1ResetVector, Format.X16),
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new RegEntry("$2209", "S-CPU Control", null),
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new RegEntry("$2209.0-3", "Message", sa1.CpuMessageReceived, Format.X8),
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new RegEntry("$2209.4", "Use NMI Vector", sa1.UseCpuNmiVector),
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new RegEntry("$2209.6", "Use IRQ Vector", sa1.UseCpuIrqVector),
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new RegEntry("$2209.7", "IRQ Requested", sa1.CpuIrqRequested),
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new RegEntry("$220A", "SA-1 CPU Interrupt Enable", null),
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new RegEntry("$220A.4", "SA-1 NMI Enabled", sa1.Sa1NmiEnabled),
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new RegEntry("$220A.5", "DMA IRQ Enabled", sa1.DmaIrqEnabled),
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new RegEntry("$220A.6", "Timer IRQ Enabled", sa1.TimerIrqEnabled),
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new RegEntry("$220A.7", "SA-1 IRQ Enabled", sa1.Sa1IrqEnabled),
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new RegEntry("$220B", "S-CPU Interrupt Clear", null),
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new RegEntry("$220B.4", "SA-1 NMI Requested", sa1.Sa1NmiRequested),
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new RegEntry("$220B.5", "DMA IRQ Flag", sa1.DmaIrqFlag),
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new RegEntry("$220B.7", "SA-1 IRQ Requested", sa1.Sa1IrqRequested),
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new RegEntry("$220C/D", "S-CPU NMI Vector", sa1.CpuNmiVector, Format.X16),
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new RegEntry("$220E/F", "S-CPU IRQ Vector", sa1.CpuIrqVector, Format.X16),
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new RegEntry("$2210", "H/V Timer Control", null),
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new RegEntry("$2210.0", "Horizontal Timer Enabled", sa1.HorizontalTimerEnabled),
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new RegEntry("$2210.1", "Vertical Timer Enabled", sa1.VerticalTimerEnabled),
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new RegEntry("$2210.7", "Linear Timer", sa1.UseLinearTimer),
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new RegEntry("$2212/3", "H-Timer", sa1.HTimer, Format.X16),
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new RegEntry("$2214/5", "V-Timer", sa1.VTimer, Format.X16),
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new RegEntry("", "ROM/BWRAM/IRAM Mappings", null),
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new RegEntry("$2220", "MMC Bank C", sa1.Banks[0], Format.X8),
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new RegEntry("$2221", "MMC Bank D", sa1.Banks[1], Format.X8),
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new RegEntry("$2222", "MMC Bank E", sa1.Banks[2], Format.X8),
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new RegEntry("$2223", "MMC Bank F", sa1.Banks[3], Format.X8),
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new RegEntry("$2224", "S-CPU BW-RAM Bank", sa1.CpuBwBank, Format.X8),
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new RegEntry("$2225.0-6", "SA-1 CPU BW-RAM Bank", sa1.Sa1BwBank, Format.X8),
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new RegEntry("$2225.7", "SA-1 CPU BW-RAM Mode", sa1.Sa1BwMode, Format.X8),
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new RegEntry("$2226.7", "S-CPU BW-RAM Write Enabled", sa1.CpuBwWriteEnabled),
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new RegEntry("$2227.7", "SA-1 BW-RAM Write Enabled", sa1.Sa1BwWriteEnabled),
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new RegEntry("$2228.0-3", "S-CPU BW-RAM Write Protected Area", sa1.BwWriteProtectedArea, Format.X8),
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new RegEntry("$2229", "S-CPU I-RAM Write Protection", sa1.CpuIRamWriteProtect, Format.X8),
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new RegEntry("$222A", "SA-1 CPU I-RAM Write Protection", sa1.Sa1IRamWriteProtect, Format.X8),
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new RegEntry("$2230", "DMA Control", null),
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new RegEntry("$2230.0-1", "DMA Source Device", sa1.DmaSrcDevice.ToString()),
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new RegEntry("$2230.2-3", "DMA Destination Device", sa1.DmaDestDevice.ToString()),
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new RegEntry("$2230.4", "Automatic DMA Character Conversion", sa1.DmaCharConvAuto),
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new RegEntry("$2230.5", "DMA Character Conversion", sa1.DmaCharConv),
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new RegEntry("$2230.6", "DMA Priority", sa1.DmaPriority),
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new RegEntry("$2230.7", "DMA Enabled", sa1.DmaEnabled),
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new RegEntry("$2231.0-1", "Character Format (BPP)", sa1.CharConvBpp, Format.D),
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new RegEntry("$2231.2-5", "Character Conversion Width", sa1.CharConvWidth, Format.X8),
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new RegEntry("$2231.7", "Character DMA Active", sa1.CharConvDmaActive),
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new RegEntry("$2232/3/4", "DMA Source Address", sa1.DmaSrcAddr, Format.X24),
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new RegEntry("$2235/6/7", "DMA Destination Address", sa1.DmaDestAddr, Format.X24),
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new RegEntry("$2238/9", "DMA Size", sa1.DmaSize, Format.X16),
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new RegEntry("$223F.7", "BW-RAM 2 bpp mode", sa1.BwRam2BppMode)
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};
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entries.Add(new RegEntry("", "Bitmap Register File", null));
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for(int i = 0; i < 8; i++) {
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entries.Add(new RegEntry("$224" + i, "BRF #" + i, sa1.BitmapRegister1[i]));
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}
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for(int i = 0; i < 8; i++) {
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entries.Add(new RegEntry("$224" + (8 + i).ToString("X"), "BRF #" + (i+8), sa1.BitmapRegister2[i]));
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}
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entries.AddRange(new List<RegEntry>() {
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new RegEntry("", "Math Registers", null),
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new RegEntry("$2250.0-1", "Math Operation", sa1.MathOp.ToString()),
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new RegEntry("$2251/2", "Multiplicand/Dividend", sa1.MultiplicandDividend, Format.X16),
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new RegEntry("$2253/4", "Multiplier/Divisor", sa1.MultiplierDivisor, Format.X16),
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new RegEntry("", "Variable Length Registers", null),
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new RegEntry("$2258", "Variable Length Bit Processing", null),
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new RegEntry("$2258.0-3", "Variable Length Bit Count", sa1.VarLenBitCount, Format.X8),
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new RegEntry("$2258.7", "Variable Length Auto-Increment", sa1.VarLenAutoInc),
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new RegEntry("$2259/A/B", "Variable Length Address", sa1.VarLenAddress, Format.X24),
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new RegEntry("$2300", "S-CPU Status Flags", null),
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new RegEntry("$2300.0-3", "Message Received", sa1.CpuMessageReceived, Format.X8),
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new RegEntry("$2300.4", "Use NMI Vector", sa1.UseCpuNmiVector),
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new RegEntry("$2300.5", "Character Conversion IRQ Flag", sa1.CharConvIrqFlag),
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new RegEntry("$2300.6", "Use IRQ Vector", sa1.UseCpuIrqVector),
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new RegEntry("$2300.7", "IRQ Requested", sa1.CpuIrqRequested),
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new RegEntry("$2301", "SA-1 Status Flags", null),
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new RegEntry("$2301.0-3", "Message Received", sa1.Sa1MessageReceived, Format.X8),
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new RegEntry("$2301.4", "NMI Requested", sa1.Sa1NmiRequested),
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new RegEntry("$2301.5", "DMA IRQ Flag", sa1.DmaIrqFlag),
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new RegEntry("$2301.7", "IRQ Requested", sa1.Sa1IrqRequested),
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new RegEntry("$2302/3", "SA-1 H-Counter", 0, Format.X16),
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new RegEntry("$2304/5", "SA-1 V-Counter", 0, Format.X16),
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new RegEntry("$2306/7/8/9/A", "Math Result", sa1.MathOpResult),
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new RegEntry("$230B.7", "Math Overflow", sa1.MathOverflow)
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});
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ctrlCoprocessor.UpdateState(entries);
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}
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}
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}
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@ -470,7 +470,7 @@ namespace Mesen.GUI.Debugger
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case CpuType.Cpu: ctrlCpuStatus.UpdateStatus(state.Cpu); break;
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case CpuType.Spc: ctrlSpcStatus.UpdateStatus(state.Spc); break;
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case CpuType.NecDsp: ctrlNecDspStatus.UpdateStatus(state.NecDsp); break;
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case CpuType.Sa1: ctrlCpuStatus.UpdateStatus(state.Sa1); break;
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case CpuType.Sa1: ctrlCpuStatus.UpdateStatus(state.Sa1.Cpu); break;
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case CpuType.Gsu: ctrlGsuStatus.UpdateStatus(state.Gsu); break;
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case CpuType.Cx4: ctrlCx4Status.UpdateStatus(state.Cx4); break;
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default: throw new Exception("Unsupported CPU type");
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@ -572,7 +572,7 @@ namespace Mesen.GUI.Debugger
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case CpuType.Cpu: activeAddress = (int)((state.Cpu.K << 16) | state.Cpu.PC); break;
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case CpuType.Spc: activeAddress = (int)state.Spc.PC; break;
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case CpuType.NecDsp: activeAddress = (int)(state.NecDsp.PC * 3); break;
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case CpuType.Sa1: activeAddress = (int)((state.Sa1.K << 16) | state.Sa1.PC); break;
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case CpuType.Sa1: activeAddress = (int)((state.Sa1.Cpu.K << 16) | state.Sa1.Cpu.PC); break;
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case CpuType.Gsu: activeAddress = (int)((state.Gsu.ProgramBank << 16) | state.Gsu.R[15]); break;
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case CpuType.Cx4: activeAddress = (int)((state.Cx4.Cache.Address[state.Cx4.Cache.Page] + (state.Cx4.PC * 2)) & 0xFFFFFF); break;
|
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default: throw new Exception("Unsupported cpu type");
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ namespace Mesen.GUI
|
|||
DirectPage = 0x20,
|
||||
Overflow = 0x40,
|
||||
Negative = 0x80
|
||||
};
|
||||
}
|
||||
|
||||
public struct CpuState
|
||||
{
|
||||
|
|
@ -71,7 +71,7 @@ namespace Mesen.GUI
|
|||
public byte IrqSource;
|
||||
public byte PrevIrqSource;
|
||||
public CpuStopState StopState;
|
||||
};
|
||||
}
|
||||
|
||||
public struct PpuState
|
||||
{
|
||||
|
|
@ -144,7 +144,7 @@ namespace Mesen.GUI
|
|||
[MarshalAs(UnmanagedType.I1)] public bool ColorMathSubstractMode;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool ColorMathHalveResult;
|
||||
public UInt16 FixedColor;
|
||||
};
|
||||
}
|
||||
|
||||
public struct LayerConfig
|
||||
{
|
||||
|
|
@ -253,7 +253,7 @@ namespace Mesen.GUI
|
|||
public SpcTimer Timer0;
|
||||
public SpcTimer Timer1;
|
||||
public SpcTimer Timer2;
|
||||
};
|
||||
}
|
||||
|
||||
public struct DspState
|
||||
{
|
||||
|
|
@ -307,7 +307,7 @@ namespace Mesen.GUI
|
|||
[MarshalAs(UnmanagedType.I1)] public bool ImmHigh;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool Prefix;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool Irq;
|
||||
};
|
||||
}
|
||||
|
||||
public struct GsuPixelCache
|
||||
{
|
||||
|
|
@ -316,7 +316,7 @@ namespace Mesen.GUI
|
|||
[MarshalAs(UnmanagedType.ByValArray, SizeConst = 8)]
|
||||
public byte[] Pixels;
|
||||
public byte ValidBits;
|
||||
};
|
||||
}
|
||||
|
||||
public struct GsuState
|
||||
{
|
||||
|
|
@ -370,7 +370,7 @@ namespace Mesen.GUI
|
|||
|
||||
public GsuPixelCache PrimaryCache;
|
||||
public GsuPixelCache SecondaryCache;
|
||||
};
|
||||
}
|
||||
|
||||
public struct Cx4Dma
|
||||
{
|
||||
|
|
@ -379,13 +379,13 @@ namespace Mesen.GUI
|
|||
public UInt16 Length;
|
||||
public UInt32 Pos;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool Enabled;
|
||||
};
|
||||
}
|
||||
|
||||
public struct Cx4Suspend
|
||||
{
|
||||
public UInt32 Duration;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool Enabled;
|
||||
};
|
||||
}
|
||||
|
||||
public struct Cx4Cache
|
||||
{
|
||||
|
|
@ -402,7 +402,7 @@ namespace Mesen.GUI
|
|||
public UInt16 ProgramBank;
|
||||
public byte ProgramCounter;
|
||||
public UInt16 Pos;
|
||||
};
|
||||
}
|
||||
|
||||
public struct Cx4Bus
|
||||
{
|
||||
|
|
@ -411,7 +411,7 @@ namespace Mesen.GUI
|
|||
[MarshalAs(UnmanagedType.I1)] public bool Writing;
|
||||
public byte DelayCycles;
|
||||
public UInt32 Address;
|
||||
};
|
||||
}
|
||||
|
||||
public struct Cx4State
|
||||
{
|
||||
|
|
@ -462,7 +462,122 @@ namespace Mesen.GUI
|
|||
|
||||
[MarshalAs(UnmanagedType.ByValArray, SizeConst = 0x20)]
|
||||
public byte[] Vectors;
|
||||
};
|
||||
}
|
||||
|
||||
public struct Sa1State
|
||||
{
|
||||
public UInt16 Sa1ResetVector;
|
||||
public UInt16 Sa1IrqVector;
|
||||
public UInt16 Sa1NmiVector;
|
||||
|
||||
[MarshalAs(UnmanagedType.I1)] public bool Sa1IrqRequested;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool Sa1IrqEnabled;
|
||||
|
||||
[MarshalAs(UnmanagedType.I1)] public bool Sa1NmiRequested;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool Sa1NmiEnabled;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool Sa1Wait;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool Sa1Reset;
|
||||
|
||||
[MarshalAs(UnmanagedType.I1)] public bool DmaIrqEnabled;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool TimerIrqEnabled;
|
||||
|
||||
public byte Sa1MessageReceived;
|
||||
public byte CpuMessageReceived;
|
||||
|
||||
public UInt16 CpuIrqVector;
|
||||
public UInt16 CpuNmiVector;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool UseCpuIrqVector;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool UseCpuNmiVector;
|
||||
|
||||
[MarshalAs(UnmanagedType.I1)] public bool CpuIrqRequested;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool CpuIrqEnabled;
|
||||
|
||||
[MarshalAs(UnmanagedType.I1)] public bool CharConvIrqFlag;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool CharConvIrqEnabled;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool CharConvDmaActive;
|
||||
public byte CharConvBpp;
|
||||
public byte CharConvFormat;
|
||||
public byte CharConvWidth;
|
||||
public byte CharConvCounter;
|
||||
|
||||
public byte CpuBwBank;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool CpuBwWriteEnabled;
|
||||
|
||||
public byte Sa1BwBank;
|
||||
public byte Sa1BwMode;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool Sa1BwWriteEnabled;
|
||||
public byte BwWriteProtectedArea;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool BwRam2BppMode;
|
||||
|
||||
[MarshalAs(UnmanagedType.ByValArray, SizeConst = 8)]
|
||||
public byte[] BitmapRegister1;
|
||||
[MarshalAs(UnmanagedType.ByValArray, SizeConst = 8)]
|
||||
public byte[] BitmapRegister2;
|
||||
|
||||
public byte CpuIRamWriteProtect;
|
||||
public byte Sa1IRamWriteProtect;
|
||||
|
||||
public UInt32 DmaSrcAddr;
|
||||
public UInt32 DmaDestAddr;
|
||||
public UInt16 DmaSize;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool DmaEnabled;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool DmaPriority;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool DmaCharConv;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool DmaCharConvAuto;
|
||||
public Sa1DmaDestDevice DmaDestDevice;
|
||||
public Sa1DmaSrcDevice DmaSrcDevice;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool DmaRunning;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool DmaIrqFlag;
|
||||
|
||||
[MarshalAs(UnmanagedType.I1)] public bool HorizontalTimerEnabled;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool VerticalTimerEnabled;
|
||||
[MarshalAs(UnmanagedType.I1)] public bool UseLinearTimer;
|
||||
|
||||
public UInt16 HTimer;
|
||||
public UInt16 VTimer;
|
||||
public UInt32 LinearTimerValue;
|
||||
|
||||
public Sa1MathOp MathOp;
|
||||
public UInt16 MultiplicandDividend;
|
||||
public UInt16 MultiplierDivisor;
|
||||
public UInt64 MathOpResult;
|
||||
public byte MathOverflow;
|
||||
|
||||
[MarshalAs(UnmanagedType.I1)] public bool VarLenAutoInc;
|
||||
public byte VarLenBitCount;
|
||||
public UInt32 VarLenAddress;
|
||||
public byte VarLenCurrentBit;
|
||||
|
||||
[MarshalAs(UnmanagedType.ByValArray, SizeConst = 4)]
|
||||
public byte[] Banks;
|
||||
}
|
||||
|
||||
public struct DebugSa1State
|
||||
{
|
||||
public CpuState Cpu;
|
||||
public Sa1State Sa1;
|
||||
}
|
||||
|
||||
public enum Sa1MathOp
|
||||
{
|
||||
Mul = 0,
|
||||
Div = 1,
|
||||
Sum = 2
|
||||
}
|
||||
|
||||
public enum Sa1DmaSrcDevice
|
||||
{
|
||||
PrgRom = 0,
|
||||
BwRam = 1,
|
||||
InternalRam = 2,
|
||||
Reserved = 3
|
||||
}
|
||||
|
||||
public enum Sa1DmaDestDevice
|
||||
{
|
||||
InternalRam = 0,
|
||||
BwRam = 1
|
||||
}
|
||||
|
||||
public struct AluState
|
||||
{
|
||||
|
|
@ -473,7 +588,7 @@ namespace Mesen.GUI
|
|||
public UInt16 Dividend;
|
||||
public byte Divisor;
|
||||
public UInt16 DivResult;
|
||||
};
|
||||
}
|
||||
|
||||
public struct InternalRegisterState
|
||||
{
|
||||
|
|
@ -490,7 +605,7 @@ namespace Mesen.GUI
|
|||
|
||||
[MarshalAs(UnmanagedType.ByValArray, SizeConst = 4)]
|
||||
public UInt16[] ControllerData;
|
||||
};
|
||||
}
|
||||
|
||||
public struct DebugState
|
||||
{
|
||||
|
|
@ -500,7 +615,7 @@ namespace Mesen.GUI
|
|||
public SpcState Spc;
|
||||
public DspState Dsp;
|
||||
public NecDspState NecDsp;
|
||||
public CpuState Sa1;
|
||||
public DebugSa1State Sa1;
|
||||
public GsuState Gsu;
|
||||
public Cx4State Cx4;
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue