empathicqubit/Mesen-SX
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

CPU: Fixed NMI logic/vector & JML instruction ($5C)

Browse source
This commit is contained in:
Sour 2019-02-15 00:09:46 -05:00
parent 0f657ccf63
commit 829f4e23c9
3 changed files with 7 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
Core/Cpu.Instructions.cpp
View file

@ -425,7 +425,7 @@ Interrupts
void Cpu::ProcessInterrupt(uint16_t vector)
{
if(_state.EmulationMode) {
PushWord(_state.PC + 1);
PushWord(_state.PC);
PushByte(_state.PS | 0x20);
SetFlags(ProcFlags::IrqDisable);
@ -434,12 +434,13 @@ void Cpu::ProcessInterrupt(uint16_t vector)
_state.PC = ReadDataWord(vector);
} else {
PushByte(_state.K);
PushWord(_state.PC + 1);
PushWord(_state.PC);
PushByte(_state.PS);
SetFlags(ProcFlags::IrqDisable);
ClearFlags(ProcFlags::Decimal);
_state.K = 0;
_state.PC = ReadDataWord(vector);
}
}

4
Core/Cpu.cpp
View file

@ -13,7 +13,7 @@ Cpu::Cpu(shared_ptr<MemoryManager> memoryManager)
&C::JSR, &C::AND, &C::JSL, &C::AND, &C::BIT, &C::AND, &C::ROL, &C::AND, &C::PLP, &C::AND, &C::ROL, &C::PLD, &C::BIT, &C::AND, &C::ROL, &C::AND, // 2
&C::BMI, &C::AND, &C::AND, &C::AND, &C::BIT, &C::AND, &C::ROL, &C::AND, &C::SEC, &C::AND, &C::DEC, &C::TSC, &C::BIT, &C::AND, &C::ROL, &C::AND, // 3
&C::RTI, &C::EOR, &C::WDM, &C::EOR, &C::MVP, &C::EOR, &C::LSR, &C::EOR, &C::PHA, &C::EOR, &C::LSR, &C::PHK, &C::JMP, &C::EOR, &C::LSR, &C::EOR, // 4
&C::BVC, &C::EOR, &C::EOR, &C::EOR, &C::MVN, &C::EOR, &C::LSR, &C::EOR, &C::CLI, &C::EOR, &C::PHY, &C::TCD, &C::JMP, &C::EOR, &C::LSR, &C::EOR, // 5
&C::BVC, &C::EOR, &C::EOR, &C::EOR, &C::MVN, &C::EOR, &C::LSR, &C::EOR, &C::CLI, &C::EOR, &C::PHY, &C::TCD, &C::JML, &C::EOR, &C::LSR, &C::EOR, // 5
&C::RTS, &C::ADC, &C::PER, &C::ADC, &C::STZ, &C::ADC, &C::ROR, &C::ADC, &C::PLA, &C::ADC, &C::ROR, &C::RTL, &C::JMP, &C::ADC, &C::ROR, &C::ADC, // 6
&C::BVS, &C::ADC, &C::ADC, &C::ADC, &C::STZ, &C::ADC, &C::ROR, &C::ADC, &C::SEI, &C::ADC, &C::PLY, &C::TDC, &C::JMP, &C::ADC, &C::ROR, &C::ADC, // 7
&C::BRA, &C::STA, &C::BRL, &C::STA, &C::STY, &C::STA, &C::STX, &C::STA, &C::DEY, &C::BIT, &C::TXA, &C::PHB, &C::STY, &C::STA, &C::STX, &C::STA, // 8
@ -78,7 +78,7 @@ void Cpu::Exec()
opCount++;
if(_nmiFlag) {
ProcessInterrupt(Cpu::NmiVector);
ProcessInterrupt(_state.EmulationMode ? Cpu::LegacyNmiVector : Cpu::NmiVector);
_nmiFlag = false;
}
}

4
Core/Cpu.h
View file

@ -13,9 +13,9 @@ public:
int32_t GetLastOperand() { return (int32_t)_operand; }
private:
static constexpr uint32_t NmiVector = 0x00FFFA;
static constexpr uint32_t NmiVector = 0x00FFEA;
static constexpr uint32_t ResetVector = 0x00FFFC;
static constexpr uint32_t IrqVector = 0x00FFFE;
static constexpr uint32_t IrqVector = 0x00FFEE;
static constexpr uint32_t AbortVector = 0x00FFE8;
static constexpr uint32_t BreakVector = 0x00FFE6;
static constexpr uint32_t CoprocessorVector = 0x00FFE4;