CPU: Implement TRB/TSB instructions

This commit is contained in:
Sour 2019-02-14 07:08:46 -05:00
parent 3cf0b0e46d
commit f979d31971
2 changed files with 31 additions and 7 deletions

View file

@ -799,9 +799,9 @@ void Cpu::STZ()
/*******************
Bit test operations
********************/
template<typename T> void Cpu::TestBits(T value)
template<typename T> void Cpu::TestBits(T value, bool alterZeroFlagOnly)
{
if(_instAddrMode <= AddrMode::ImmM) {
if(alterZeroFlagOnly) {
//"Immediate addressing only affects the z flag (with the result of the bitwise And), but does not affect the n and v flags."
if(((T)_state.A & value) == 0) {
SetFlags(ProcFlags::Zero);
@ -827,20 +827,44 @@ template<typename T> void Cpu::TestBits(T value)
void Cpu::BIT()
{
if(CheckFlag(ProcFlags::MemoryMode8)) {
TestBits<uint8_t>(GetByteValue());
TestBits<uint8_t>(GetByteValue(), _instAddrMode <= AddrMode::ImmM);
} else {
TestBits<uint16_t>(GetWordValue());
TestBits<uint16_t>(GetWordValue(), _instAddrMode <= AddrMode::ImmM);
}
}
void Cpu::TRB()
{
//TODO
if(CheckFlag(ProcFlags::MemoryMode8)) {
TestBits<uint8_t>(GetByteValue(), true);
uint8_t value = ReadData(_operand);
value &= ~_state.A;
Write(_operand, value);
} else {
TestBits<uint16_t>(GetWordValue(), true);
uint16_t value = ReadDataWord(_operand);
value &= ~_state.A;
WriteWord(_operand, value);
}
}
void Cpu::TSB()
{
//TODO
if(CheckFlag(ProcFlags::MemoryMode8)) {
TestBits<uint8_t>(GetByteValue(), true);
uint8_t value = ReadData(_operand);
value |= _state.A;
Write(_operand, value);
} else {
TestBits<uint16_t>(GetWordValue(), true);
uint16_t value = ReadDataWord(_operand);
value |= _state.A;
WriteWord(_operand, value);
}
}
/******************

View file

@ -205,7 +205,7 @@ private:
void STZ();
//Test bits
template<typename T> void TestBits(T value);
template<typename T> void TestBits(T value, bool alterZeroFlagOnly);
void BIT();
void TRB();