Reads done by the code should return the values at the read address, rather than returning the vector register value (fixes Gradius/Contra 3 SA-1 romhacks that are known to work on hardware)
-Fixed I-RAM access speed while main CPU is DMAing to I-RAM
-Fixed missing extra cycle on BRL
-Fixed idle SA-1 cycles (incorrectly) taking more than 1 cycle during bus conflicts
-Fixed branch instructions to apply cycle penalties based on the destination address' type (rather than the source address)
