2 commits

Author	SHA1	Message	Date
Sour	67b286a16f	SA1: Improved timings (bus conflicts, etc.) ... -Fixed I-RAM access speed while main CPU is DMAing to I-RAM -Fixed missing extra cycle on BRL -Fixed idle SA-1 cycles (incorrectly) taking more than 1 cycle during bus conflicts -Fixed branch instructions to apply cycle penalties based on the destination address' type (rather than the source address)	2019-11-25 21:01:21 -05:00
Sour	fe470dd87a	SA-1 support (still missing a few rarely used features)	2019-07-25 22:22:09 -04:00

Renamed from Core/Cpu.Instructions.cpp (Browse further)