5 commits

Author	SHA1	Message	Date
Sour	67b286a16f	SA1: Improved timings (bus conflicts, etc.) ... -Fixed I-RAM access speed while main CPU is DMAing to I-RAM -Fixed missing extra cycle on BRL -Fixed idle SA-1 cycles (incorrectly) taking more than 1 cycle during bus conflicts -Fixed branch instructions to apply cycle penalties based on the destination address' type (rather than the source address)	2019-11-25 21:01:21 -05:00
Sour	efe157cfcb	SA-1: Added variable bit length data support	2019-08-09 00:04:01 -04:00
Sour	22d4f58eae	SA-1: Add support for both character conversion types	2019-08-08 23:05:24 -04:00
Sour	33cee67e61	Added GSU (Super FX) support	2019-07-30 22:43:32 -04:00
Sour	fe470dd87a	SA-1 support (still missing a few rarely used features)	2019-07-25 22:22:09 -04:00