Commit graph

20 commits

Author SHA1 Message Date
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02425d7453 DMA: Added delay values for DMA/HDMA 2019-02-21 23:35:51 -05:00
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0b7ad7c0db CPU: Added all idle cycles + added DRAM refresh delay 2019-02-21 22:10:41 -05:00
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97c7d06156 Fixed throw syntax 2019-02-21 18:18:25 -05:00
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170a33af49 CPU: Implemented FastROM register 2019-02-21 18:12:44 -05:00
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b2af226467 Code optimization 2019-02-21 17:17:55 -05:00
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5952fcd3f5 DMA: Implemented DMA register reads 2019-02-21 07:55:53 -05:00
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68e7617c95 PPU: Implemented VRAM/CGRAM reads + H/V offset data latches
+ Implemented work ram read register
2019-02-21 07:27:47 -05:00
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221bc44700 DMA: Added support for HDMA (incorrect timings) 2019-02-19 21:09:12 -05:00
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b806b3d96e Core: Added SNES controller support 2019-02-17 20:29:29 -05:00
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aaf147b53b Refactor internal CPU registers + implement division register 2019-02-17 15:37:31 -05:00
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93e8fd9d5e Core: Fixed for memory mappings, implemented multiplication register, added logging to help debugging missing functionalities 2019-02-17 14:42:35 -05:00
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bdc57286e7 SPC: Integrate blargg's SPC emulation library
Sound still doesn't work, however.
2019-02-16 11:23:01 -05:00
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e257db4def Fixed memory leaks 2019-02-16 01:16:57 -05:00
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6d22b920b8 Debugger: Added hex editor 2019-02-15 21:33:13 -05:00
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0f657ccf63 DMA: Refactoring + improvements/fixes 2019-02-15 00:08:50 -05:00
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b33380a95e CPU: Fixed bugs with PEA/PEI/PER 2019-02-14 19:00:17 -05:00
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69cf69fa6f PPU: Implement some of the registers 2019-02-13 18:44:39 -05:00
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522372a365 Fixed addressing bugs, added PPU stub, improved trace logger output, split CPU instructions to another file 2019-02-13 13:32:51 -05:00
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5c19584019 Imported some code from Mesen (video, audio, UI, etc.) + basic trace logger/step functionality 2019-02-12 22:13:09 -05:00
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5e7eebe078 CPU: Fixed immediate more 8-bit vs 16-bit logic
+ Added bare minimum logic to load a rom and start executing it
2019-02-11 22:41:34 -05:00