735 lines
No EOL
15 KiB
C++
735 lines
No EOL
15 KiB
C++
#include "stdafx.h"
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#include "Gsu.h"
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#include "Cpu.h"
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#include "MemoryManager.h"
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void Gsu::STOP()
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{
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if(!_state.IrqDisabled) {
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_state.SFR.Irq = true;
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_cpu->SetIrqSource(IrqSource::Coprocessor);
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}
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_state.ProgramReadBuffer = 0x01; //Run a NOP first when the GSU is restarted
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_state.SFR.Running = false;
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ResetFlags();
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UpdateRunningState();
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}
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void Gsu::NOP()
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{
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ResetFlags();
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}
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void Gsu::CACHE()
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{
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if(_state.CacheBase != (_state.R[15] & 0xFFF0)) {
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_state.CacheBase = _state.R[15] & 0xFFF0;
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InvalidateCache();
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}
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ResetFlags();
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}
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void Gsu::Branch(bool branch)
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{
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int8_t offset = (int8_t)ReadOperand();
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if(branch) {
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WriteRegister(15, _state.R[15] + offset);
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}
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}
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void Gsu::BRA()
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{
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Branch(true);
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}
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void Gsu::BLT()
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{
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Branch(_state.SFR.Sign == _state.SFR.Overflow);
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}
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void Gsu::BGE()
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{
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Branch(_state.SFR.Sign != _state.SFR.Overflow);
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}
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void Gsu::BNE()
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{
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Branch(!_state.SFR.Zero);
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}
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void Gsu::BEQ()
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{
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Branch(_state.SFR.Zero);
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}
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void Gsu::BPL()
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{
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Branch(!_state.SFR.Sign);
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}
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void Gsu::BMI()
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{
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Branch(_state.SFR.Sign);
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}
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void Gsu::BCC()
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{
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Branch(!_state.SFR.Carry);
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}
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void Gsu::BCS()
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{
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Branch(_state.SFR.Carry);
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}
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void Gsu::BCV()
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{
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Branch(!_state.SFR.Overflow);
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}
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void Gsu::BVS()
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{
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Branch(_state.SFR.Overflow);
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}
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void Gsu::JMP(uint8_t reg)
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{
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if(_state.SFR.Alt1) {
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//LJMP
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_state.ProgramBank = _state.R[reg] & 0x7F;
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WriteRegister(15, ReadSrcReg());
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_state.CacheBase = _state.R[15] & 0xFFF0;
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InvalidateCache();
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} else {
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//JMP
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WriteRegister(15, _state.R[reg]);
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}
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ResetFlags();
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}
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void Gsu::TO(uint8_t reg)
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{
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if(_state.SFR.Prefix) {
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//MOVE
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WriteRegister(reg, ReadSrcReg());
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ResetFlags();
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} else {
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//TO
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_state.DestReg = reg;
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}
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}
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void Gsu::FROM(uint8_t reg)
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{
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if(_state.SFR.Prefix) {
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//MOVES
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WriteDestReg(_state.R[reg]);
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_state.SFR.Overflow = (_state.R[reg] & 0x80) != 0;
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_state.SFR.Sign = (_state.R[reg] & 0x8000) != 0;
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_state.SFR.Zero = (_state.R[reg] == 0);
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ResetFlags();
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} else {
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//FROM
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_state.SrcReg = reg;
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}
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}
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void Gsu::WITH(uint8_t reg)
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{
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_state.SrcReg = reg;
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_state.DestReg = reg;
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_state.SFR.Prefix = true;
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}
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void Gsu::STORE(uint8_t reg)
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{
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_state.RamAddress = _state.R[reg];
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WriteRam(_state.RamAddress, (uint8_t)ReadSrcReg());
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if(!_state.SFR.Alt1) {
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WriteRam(_state.RamAddress ^ 0x01, ReadSrcReg() >> 8);
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}
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ResetFlags();
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}
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void Gsu::LOAD(uint8_t reg)
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{
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_state.RamAddress = _state.R[reg];
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uint16_t value = ReadRamBuffer(_state.RamAddress);
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if(!_state.SFR.Alt1) {
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value |= ReadRamBuffer(_state.RamAddress ^ 0x01) << 8;
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}
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WriteDestReg(value);
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ResetFlags();
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}
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void Gsu::LOOP()
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{
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_state.R[12]--;
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_state.SFR.Zero = (_state.R[12] == 0);
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_state.SFR.Sign = (_state.R[12] & 0x8000) != 0;
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//Loop until counter hits zero
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if(!_state.SFR.Zero) {
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WriteRegister(15, _state.R[13]);
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}
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ResetFlags();
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}
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void Gsu::ALT1()
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{
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_state.SFR.Prefix = false;
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_state.SFR.Alt1 = true;
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}
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void Gsu::ALT2()
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{
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_state.SFR.Prefix = false;
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_state.SFR.Alt2 = true;
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}
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void Gsu::ALT3()
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{
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_state.SFR.Prefix = false;
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_state.SFR.Alt1 = true;
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_state.SFR.Alt2 = true;
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}
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void Gsu::MERGE()
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{
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uint16_t value = (_state.R[7] & 0xFF00) | (_state.R[8] >> 8);
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WriteDestReg(value);
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_state.SFR.Carry = (value & 0xE0E0) != 0;
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_state.SFR.Overflow = (value & 0xC0C0) != 0;
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_state.SFR.Sign = (value & 0x8080) != 0;
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_state.SFR.Zero = (value & 0xF0F0) != 0;
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ResetFlags();
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}
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void Gsu::SWAP()
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{
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uint16_t value = (ReadSrcReg() >> 8) | (ReadSrcReg() << 8);
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WriteDestReg(value);
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_state.SFR.Zero = value == 0;
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_state.SFR.Sign = (value & 0x8000) != 0;
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ResetFlags();
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}
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void Gsu::Add(uint8_t reg)
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{
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uint16_t operand;
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if(_state.SFR.Alt2) {
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//Immediate value
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operand = reg;
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} else {
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operand = _state.R[reg];
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}
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uint32_t result = ReadSrcReg() + operand;
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if(_state.SFR.Alt1) {
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//ADC - Add with carry
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result += (uint8_t)_state.SFR.Carry;
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}
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_state.SFR.Carry = (result & 0x10000) != 0;
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_state.SFR.Overflow = ~(ReadSrcReg() ^ operand) & (operand ^ result) & 0x8000;
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_state.SFR.Sign = (result & 0x8000) != 0;
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_state.SFR.Zero = (result & 0xFFFF) == 0;
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WriteDestReg(result);
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ResetFlags();
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}
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void Gsu::SubCompare(uint8_t reg)
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{
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uint16_t operand;
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if(_state.SFR.Alt2 && !_state.SFR.Alt1) {
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//Immediate value, SUB #val
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operand = reg;
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} else {
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operand = _state.R[reg];
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}
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int32_t result = ReadSrcReg() - operand;
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if(!_state.SFR.Alt2 && _state.SFR.Alt1) {
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//SBC - SUB with carry
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result -= _state.SFR.Carry ? 0 : 1;
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}
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_state.SFR.Carry = (result >= 0);
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_state.SFR.Overflow = ((ReadSrcReg() ^ operand) & (ReadSrcReg() ^ result) & 0x8000) != 0;
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_state.SFR.Sign = (result & 0x8000) != 0;
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_state.SFR.Zero = (result & 0xFFFF) == 0;
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if(!_state.SFR.Alt2 || !_state.SFR.Alt1) {
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//SUB/SBC, other CMP (and no write occurs for CMP)
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WriteDestReg(result);
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}
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ResetFlags();
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}
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void Gsu::MULT(uint8_t reg)
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{
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uint16_t operand;
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if(_state.SFR.Alt2) {
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//Immediate value
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operand = reg;
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} else {
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operand = _state.R[reg];
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}
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uint16_t value;
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if(_state.SFR.Alt1) {
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//UMULT - Unsigned multiply
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value = (uint16_t)((uint8_t)ReadSrcReg() * (uint8_t)operand);
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} else {
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//MULT - Signed multiply
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value = (uint16_t)((int8_t)ReadSrcReg() * (int8_t)operand);
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}
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WriteDestReg(value);
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_state.SFR.Sign = (value & 0x8000) != 0;
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_state.SFR.Zero = value == 0;
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ResetFlags();
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Step(_state.HighSpeedMode ? 1 : 2);
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}
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void Gsu::FMultLMult()
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{
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uint32_t multResult = (int16_t)ReadSrcReg() * (int16_t)_state.R[6];
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if(_state.SFR.Alt1) {
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//LMULT - "16x16 signed multiply", LSB in R4, MSB in DREG
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_state.R[4] = multResult;
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}
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uint16_t value = multResult >> 16;
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WriteDestReg(value);
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_state.SFR.Carry = (multResult & 0x8000);
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_state.SFR.Sign = (value & 0x8000);
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_state.SFR.Zero = (value == 0);
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ResetFlags();
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Step((_state.HighSpeedMode ? 3 : 7) * (_state.ClockSelect ? 1 : 2));
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}
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void Gsu::AndBitClear(uint8_t reg)
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{
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uint16_t operand;
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if(_state.SFR.Alt2) {
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//Immediate value
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operand = reg;
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} else {
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operand = _state.R[reg];
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}
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uint16_t value;
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if(_state.SFR.Alt1) {
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//Bit clear
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value = ReadSrcReg() & ~operand;
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} else {
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//AND
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value = ReadSrcReg() & operand;
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}
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WriteDestReg(value);
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_state.SFR.Zero = value == 0;
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_state.SFR.Sign = (value & 0x8000) != 0;
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ResetFlags();
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}
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void Gsu::SBK()
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{
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//"Store word data, last RAM address used"
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WriteRam(_state.RamAddress, (uint8_t)ReadSrcReg());
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WriteRam(_state.RamAddress ^ 1, ReadSrcReg() >> 8);
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ResetFlags();
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}
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void Gsu::LINK(uint8_t value)
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{
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//"Link Return Address"
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_state.R[11] = _state.R[15] + value;
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ResetFlags();
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}
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void Gsu::SignExtend()
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{
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int16_t value = (int8_t)ReadSrcReg();
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WriteDestReg((uint16_t)value);
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_state.SFR.Zero = value == 0;
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_state.SFR.Sign = (value & 0x8000) != 0;
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ResetFlags();
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}
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void Gsu::NOT()
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{
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uint16_t value = ~ReadSrcReg();
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WriteDestReg(value);
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_state.SFR.Zero = value == 0;
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_state.SFR.Sign = (value & 0x8000) != 0;
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ResetFlags();
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}
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void Gsu::LSR()
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{
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uint16_t src = ReadSrcReg();
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_state.SFR.Carry = (src & 0x01) != 0;
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uint16_t dst = src >> 1;
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WriteDestReg(dst);
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_state.SFR.Zero = dst == 0;
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_state.SFR.Sign = (dst & 0x8000) != 0;
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ResetFlags();
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}
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void Gsu::ROL()
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{
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uint16_t src = ReadSrcReg();
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uint16_t dst = (src << 1) | (uint8_t)_state.SFR.Carry;
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_state.SFR.Carry = (src & 0x8000) != 0;
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WriteDestReg(dst);
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_state.SFR.Zero = dst == 0;
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_state.SFR.Sign = (dst & 0x8000) != 0;
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ResetFlags();
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}
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void Gsu::ASR()
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{
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uint16_t src = ReadSrcReg();
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_state.SFR.Carry = (src & 0x01) != 0;
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uint16_t dst = (int16_t)src >> 1;
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if(_state.SFR.Alt1) {
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dst += (src + 1) >> 16;
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}
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WriteDestReg(dst);
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_state.SFR.Zero = dst == 0;
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_state.SFR.Sign = (dst & 0x8000) != 0;
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ResetFlags();
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}
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void Gsu::ROR()
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{
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uint16_t src = ReadSrcReg();
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uint16_t dst = (src >> 1) | ((int)_state.SFR.Carry << 15);
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_state.SFR.Carry = (src & 0x01) != 0;
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WriteDestReg(dst);
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_state.SFR.Zero = dst == 0;
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_state.SFR.Sign = (dst & 0x8000) != 0;
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ResetFlags();
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}
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void Gsu::LOB()
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{
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//"Value of low byte of register"
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uint8_t value = (uint8_t)ReadSrcReg();
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WriteDestReg(value);
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_state.SFR.Zero = value == 0;
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_state.SFR.Sign = (value & 0x80) != 0;
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ResetFlags();
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}
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void Gsu::HIB()
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{
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//"Value of high byte of register"
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uint8_t value = (uint8_t)(ReadSrcReg() >> 8);
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WriteDestReg(value);
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_state.SFR.Zero = value == 0;
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_state.SFR.Sign = (value & 0x80) != 0;
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ResetFlags();
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}
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void Gsu::IbtSmsLms(uint8_t reg)
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{
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if(_state.SFR.Alt1) {
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//LMS - "Load word data from RAM, short address"
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_state.RamAddress = ReadOperand() << 1;
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uint8_t lsb = ReadRamBuffer(_state.RamAddress);
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uint8_t msb = ReadRamBuffer(_state.RamAddress | 0x01);
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WriteRegister(reg, (msb << 8) | lsb);
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} else if(_state.SFR.Alt2) {
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//SMS - "Store word data to RAM, short address"
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_state.RamAddress = ReadOperand() << 1;
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WriteRam(_state.RamAddress, (uint8_t)_state.R[reg]);
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WriteRam(_state.RamAddress | 0x01, _state.R[reg] >> 8);
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} else {
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//IBT - "Load immediate byte data"
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WriteRegister(reg, (int8_t)ReadOperand());
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}
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ResetFlags();
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}
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void Gsu::IwtLmSm(uint8_t reg)
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{
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if(_state.SFR.Alt1) {
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//LM - Load memory
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_state.RamAddress = ReadOperand();
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_state.RamAddress |= ReadOperand() << 8;
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uint8_t lsb = ReadRamBuffer(_state.RamAddress);
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uint8_t msb = ReadRamBuffer(_state.RamAddress ^ 0x01);
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WriteRegister(reg, (msb << 8) | lsb);
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} else if(_state.SFR.Alt2) {
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//SM - Store Memory
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_state.RamAddress = ReadOperand();
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_state.RamAddress |= ReadOperand() << 8;
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WriteRam(_state.RamAddress, (uint8_t)_state.R[reg]);
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WriteRam(_state.RamAddress ^ 0x01, _state.R[reg] >> 8);
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} else {
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//IWT - Load immediate word
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uint8_t lsb = ReadOperand();
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uint8_t msb = ReadOperand();
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WriteRegister(reg, (msb << 8) | lsb);
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}
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ResetFlags();
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}
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void Gsu::OrXor(uint8_t operand)
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{
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uint16_t operandValue;
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if(_state.SFR.Alt2) {
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//Immediate value
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operandValue = operand;
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} else {
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//Indirect register value
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operandValue = _state.R[operand];
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}
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uint16_t value;
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if(_state.SFR.Alt1) {
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//XOR
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value = ReadSrcReg() ^ operandValue;
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} else {
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//OR
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value = ReadSrcReg() | operandValue;
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}
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WriteDestReg(value);
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_state.SFR.Zero = value == 0;
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_state.SFR.Sign = (value & 0x8000) != 0;
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ResetFlags();
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}
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void Gsu::INC(uint8_t reg)
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{
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WriteRegister(reg, _state.R[reg] + 1);
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_state.SFR.Zero = _state.R[reg] == 0;
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_state.SFR.Sign = (_state.R[reg] & 0x8000) != 0;
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ResetFlags();
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}
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void Gsu::DEC(uint8_t reg)
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{
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WriteRegister(reg, _state.R[reg] - 1);
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_state.SFR.Zero = _state.R[reg] == 0;
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_state.SFR.Sign = (_state.R[reg] & 0x8000) != 0;
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ResetFlags();
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}
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void Gsu::GetCRamBRomB()
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{
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if(!_state.SFR.Alt2) {
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//GETC - "Get byte from ROM to color register"
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_state.ColorReg = GetColor(ReadRomBuffer());
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} else if(!_state.SFR.Alt1) {
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//RAMB - "Set RAM data bank"
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WaitRamOperation();
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_state.RamBank = ReadSrcReg() & 0x01;
|
|
} else {
|
|
//ROMB - "Set ROM data bank"
|
|
WaitRomOperation();
|
|
_state.RomBank = ReadSrcReg() & 0x7F;
|
|
}
|
|
ResetFlags();
|
|
}
|
|
|
|
void Gsu::GETB()
|
|
{
|
|
if(_state.SFR.Alt2 && _state.SFR.Alt1) {
|
|
//GETBS - "Get signed byte from ROM buffer"
|
|
WriteDestReg((int8_t)ReadRomBuffer());
|
|
} else if(_state.SFR.Alt2) {
|
|
//GETBL - "Get low byte from ROM buffer"
|
|
WriteDestReg((ReadSrcReg() & 0xFF00) | ReadRomBuffer());
|
|
} else if(_state.SFR.Alt1) {
|
|
//GETBH - "Get high byte from ROM buffer"
|
|
WriteDestReg((ReadSrcReg() & 0xFF) | (ReadRomBuffer() << 8));
|
|
} else {
|
|
//GETB - "Get byte from ROM buffer"
|
|
WriteDestReg(ReadRomBuffer());
|
|
}
|
|
ResetFlags();
|
|
}
|
|
|
|
void Gsu::PlotRpix()
|
|
{
|
|
if(_state.SFR.Alt1) {
|
|
//RPIX - "Read pixel color"
|
|
uint8_t value = ReadPixel((uint8_t)_state.R[1], (uint8_t)_state.R[2]);
|
|
_state.SFR.Zero = (value == 0);
|
|
_state.SFR.Sign = (value & 0x8000);
|
|
WriteDestReg(value);
|
|
} else {
|
|
//PLOT
|
|
DrawPixel((uint8_t)_state.R[1], (uint8_t)_state.R[2]);
|
|
_state.R[1]++;
|
|
}
|
|
ResetFlags();
|
|
}
|
|
|
|
void Gsu::ColorCMode()
|
|
{
|
|
if(_state.SFR.Alt1) {
|
|
//CMODE - "Set plot mode"
|
|
uint8_t value = (uint8_t)ReadSrcReg();
|
|
_state.PlotTransparent = (value & 0x01) != 0;
|
|
_state.PlotDither = (value & 0x02) != 0;
|
|
_state.ColorHighNibble = (value & 0x04) != 0;
|
|
_state.ColorFreezeHigh = (value & 0x08) != 0;
|
|
_state.ObjMode = (value & 0x10) != 0;
|
|
} else {
|
|
//COLOR - "Set plot color"
|
|
_state.ColorReg = GetColor((uint8_t)ReadSrcReg());
|
|
}
|
|
ResetFlags();
|
|
}
|
|
|
|
uint16_t Gsu::GetTileIndex(uint8_t x, uint8_t y)
|
|
{
|
|
switch(_state.ObjMode ? 3 : _state.ScreenHeight) {
|
|
default:
|
|
case 0: return ((x & 0xF8) << 1) + ((y & 0xF8) >> 3); break;
|
|
case 1: return ((x & 0xF8) << 1) + ((x & 0xF8) >> 1) + ((y & 0xF8) >> 3); break;
|
|
case 2: return ((x & 0xF8) << 1) + ((x & 0xF8) << 0) + ((y & 0xF8) >> 3); break;
|
|
case 3: return ((y & 0x80) << 2) + ((x & 0x80) << 1) + ((y & 0x78) << 1) + ((x & 0x78) >> 3); break;
|
|
}
|
|
}
|
|
|
|
uint32_t Gsu::GetTileAddress(uint8_t x, uint8_t y)
|
|
{
|
|
uint16_t tileIndex = GetTileIndex(x, y);
|
|
return (0x700000 | (_state.ScreenBase << 10)) + (tileIndex * (_state.PlotBpp << 3)) + ((y & 0x07) * 2);
|
|
}
|
|
|
|
uint8_t Gsu::ReadPixel(uint8_t x, uint8_t y)
|
|
{
|
|
WritePixelCache(_state.SecondaryCache);
|
|
WritePixelCache(_state.PrimaryCache);
|
|
|
|
uint32_t tileAddress = GetTileAddress(x, y);
|
|
|
|
x = (x & 7) ^ 7;
|
|
|
|
uint8_t data = 0;
|
|
for(int i = 0; i < _state.PlotBpp; i++) {
|
|
//Select which byte to read/write based on the current bit (0/1, 16/17, 32/33, 48/49)
|
|
uint8_t byteOffset = ((i >> 1) << 4) + (i & 0x01);
|
|
data |= ((ReadGsu(tileAddress + byteOffset, MemoryOperationType::Read) >> x) & 1) << i;
|
|
Step(_state.ClockSelect ? 5 : 6);
|
|
}
|
|
|
|
return data;
|
|
}
|
|
|
|
bool Gsu::IsTransparentPixel()
|
|
{
|
|
uint8_t color = _state.ColorFreezeHigh ? (_state.ColorReg & 0x0F) : _state.ColorReg;
|
|
|
|
switch(_state.PlotBpp) {
|
|
default:
|
|
case 2: return (color & 0x03) == 0;
|
|
case 4: return (color & 0x0F) == 0;
|
|
case 8: return color == 0;
|
|
}
|
|
}
|
|
|
|
void Gsu::DrawPixel(uint8_t x, uint8_t y)
|
|
{
|
|
if(!_state.PlotTransparent && IsTransparentPixel()) {
|
|
return;
|
|
}
|
|
|
|
uint8_t color = _state.ColorReg;
|
|
if(_state.PlotDither && _state.PlotBpp != 8) {
|
|
if((x ^ y) & 0x01) {
|
|
color >>= 4;
|
|
}
|
|
color &= 0x0F;
|
|
}
|
|
|
|
if(_state.PrimaryCache.X != (x & 0xF8) || _state.PrimaryCache.Y != y) {
|
|
FlushPrimaryCache(x, y);
|
|
}
|
|
|
|
uint8_t xOffset = (x & 7) ^ 7;
|
|
_state.PrimaryCache.Pixels[xOffset] = color;
|
|
_state.PrimaryCache.ValidBits |= (1 << xOffset);
|
|
if(_state.PrimaryCache.ValidBits == 0xFF) {
|
|
FlushPrimaryCache(x, y);
|
|
}
|
|
}
|
|
|
|
void Gsu::FlushPrimaryCache(uint8_t x, uint8_t y)
|
|
{
|
|
WritePixelCache(_state.SecondaryCache);
|
|
_state.SecondaryCache = _state.PrimaryCache;
|
|
_state.PrimaryCache.ValidBits = 0;
|
|
_state.PrimaryCache.X = x & 0xF8;
|
|
_state.PrimaryCache.Y = y;
|
|
}
|
|
|
|
void Gsu::WritePixelCache(GsuPixelCache &cache)
|
|
{
|
|
if(cache.ValidBits == 0) {
|
|
return;
|
|
}
|
|
|
|
uint32_t tileAddress = GetTileAddress(cache.X, cache.Y);
|
|
|
|
for(int i = 0; i < _state.PlotBpp; i++) {
|
|
uint8_t value = 0;
|
|
for(int x = 0; x < 8; x++) {
|
|
value |= ((cache.Pixels[x] >> i) & 0x01) << x;
|
|
}
|
|
|
|
//Select which byte to read/write based on the current bit (0/1, 16/17, 32/33, 48/49)
|
|
uint8_t byte = ((i >> 1) << 4) + (i & 0x01);
|
|
|
|
if(cache.ValidBits != 0xFF) {
|
|
//Read the pixels in memory before to merge them before writing the cache's content to memory
|
|
Step(_state.ClockSelect ? 5 : 6);
|
|
value &= cache.ValidBits;
|
|
value |= ReadGsu(tileAddress + byte, MemoryOperationType::Read) & ~cache.ValidBits;
|
|
}
|
|
|
|
Step(_state.ClockSelect ? 5 : 6);
|
|
WaitForRamAccess();
|
|
WriteGsu(tileAddress + byte, value, MemoryOperationType::Write);
|
|
}
|
|
|
|
cache.ValidBits = 0;
|
|
}
|
|
|
|
uint8_t Gsu::GetColor(uint8_t value)
|
|
{
|
|
if(_state.ColorHighNibble) {
|
|
return (_state.ColorReg & 0xF0) | (value >> 4);
|
|
}
|
|
if(_state.ColorFreezeHigh) {
|
|
return (_state.ColorReg & 0xF0) | (value & 0x0F);
|
|
}
|
|
|
|
return value;
|
|
} |