366 lines
8.1 KiB
C++
366 lines
8.1 KiB
C++
#include "stdafx.h"
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#include "Spc.h"
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#include "Console.h"
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#include "MemoryManager.h"
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#include "SoundMixer.h"
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#include "SPC_DSP.h"
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#include "../Utilities/Serializer.h"
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Spc::Spc(shared_ptr<Console> console, vector<uint8_t> &spcRomData)
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{
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_console = console;
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_soundBuffer = new int16_t[Spc::SampleBufferSize];
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_immediateMode = false;
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_operandA = 0;
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_operandB = 0;
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_dsp.reset(new SPC_DSP());
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_dsp->init(_ram);
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_dsp->reset();
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_dsp->set_output(_soundBuffer, Spc::SampleBufferSize >> 1);
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memcpy(_spcBios, spcRomData.data(), 64);
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memset(_ram, 0, sizeof(_ram));
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_state = {};
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_state.WriteEnabled = true;
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_state.TimersEnabled = true;
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_state.RomEnabled = true;
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_state.SP = 0xFF;
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_state.PC = ReadWord(Spc::ResetVector);
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}
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Spc::~Spc()
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{
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delete[] _soundBuffer;
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}
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void Spc::Reset()
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{
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_state.Timer0.Reset();
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_state.Timer1.Reset();
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_state.Timer2.Reset();
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_state.RomEnabled = true;
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_state.Cycle = 0;
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_state.PC = ReadWord(Spc::ResetVector);
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_dsp->soft_reset();
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_dsp->set_output(_soundBuffer, Spc::SampleBufferSize >> 1);
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}
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void Spc::Idle()
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{
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IncCycleCount(-1);
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}
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void Spc::DummyRead()
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{
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Read(_state.PC);
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}
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void Spc::DummyRead(uint16_t addr)
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{
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Read(addr);
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}
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void Spc::IncCycleCount(int32_t addr)
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{
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static constexpr uint8_t cpuWait[4] = { 2, 4, 10, 20 };
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static constexpr uint8_t timerMultiplier[4] = { 2, 4, 8, 16 };
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uint8_t speedSelect;
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if(addr < 0 || ((addr & 0xFFF0) == 0x00F0) || (addr >= 0xFFC0 && _state.RomEnabled)) {
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//Use internal speed (bits 4-5) for idle cycles, register access or IPL rom access
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speedSelect = _state.InternalSpeed;
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} else {
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speedSelect = _state.ExternalSpeed;
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}
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_state.Cycle += cpuWait[speedSelect];
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_dsp->run();
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uint8_t timerInc = timerMultiplier[speedSelect];
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_state.Timer0.Run(timerInc);
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_state.Timer1.Run(timerInc);
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_state.Timer2.Run(timerInc);
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}
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uint8_t Spc::Read(uint16_t addr, MemoryOperationType type)
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{
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IncCycleCount(addr);
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if(addr >= 0xFFC0 && _state.RomEnabled) {
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return _spcBios[addr & 0x3F];
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}
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switch(addr) {
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case 0xF0: return 0;
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case 0xF1: return 0;
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case 0xF2: return _state.DspReg;
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case 0xF3: return _dsp->read(_state.DspReg & 0x7F);
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case 0xF4: return _state.CpuRegs[0];
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case 0xF5: return _state.CpuRegs[1];
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case 0xF6: return _state.CpuRegs[2];
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case 0xF7: return _state.CpuRegs[3];
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case 0xF8: return _state.RamReg[0];
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case 0xF9: return _state.RamReg[1];
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case 0xFA: return 0;
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case 0xFB: return 0;
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case 0xFC: return 0;
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case 0xFD: return _state.Timer0.GetOutput();
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case 0xFE: return _state.Timer1.GetOutput();
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case 0xFF: return _state.Timer2.GetOutput();
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}
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uint8_t value = _ram[addr];
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_console->ProcessSpcRead(addr, value, type);
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return value;
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}
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void Spc::Write(uint16_t addr, uint8_t value, MemoryOperationType type)
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{
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IncCycleCount(addr);
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//Writes always affect the underlying RAM
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if(_state.WriteEnabled) {
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_console->ProcessSpcWrite(addr, value, type);
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_ram[addr] = value;
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}
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switch(addr) {
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case 0xF0:
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if(!CheckFlag(SpcFlags::DirectPage)) {
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_state.InternalSpeed = (value >> 6) & 0x03;
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_state.ExternalSpeed = (value >> 4) & 0x03;
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_state.TimersEnabled = (value & 0x09) == 0x08;
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_state.WriteEnabled = value & 0x02;
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_dsp->setEchoWriteEnabled(_state.WriteEnabled);
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_state.Timer0.SetGlobalEnabled(_state.TimersEnabled);
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_state.Timer1.SetGlobalEnabled(_state.TimersEnabled);
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_state.Timer2.SetGlobalEnabled(_state.TimersEnabled);
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}
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break;
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case 0xF1:
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if(value & SpcControlFlags::ClearPortsA) {
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_state.CpuRegs[0] = _state.CpuRegs[1] = 0;
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}
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if(value & SpcControlFlags::ClearPortsB) {
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_state.CpuRegs[2] = _state.CpuRegs[3] = 0;
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}
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_state.Timer0.SetEnabled((value & SpcControlFlags::Timer0) != 0);
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_state.Timer1.SetEnabled((value & SpcControlFlags::Timer1) != 0);
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_state.Timer2.SetEnabled((value & SpcControlFlags::Timer2) != 0);
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_state.RomEnabled = (value & SpcControlFlags::EnableRom) != 0;
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break;
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case 0xF2: _state.DspReg = value; break;
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case 0xF3:
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if(_state.DspReg < 128) {
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_dsp->write(_state.DspReg, value);
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}
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break;
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case 0xF4: _state.OutputReg[0] = value; break;
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case 0xF5: _state.OutputReg[1] = value; break;
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case 0xF6: _state.OutputReg[2] = value; break;
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case 0xF7: _state.OutputReg[3] = value; break;
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case 0xF8: _state.RamReg[0] = value; break;
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case 0xF9: _state.RamReg[1] = value; break;
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case 0xFA: _state.Timer0.SetTarget(value); break;
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case 0xFB: _state.Timer1.SetTarget(value); break;
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case 0xFC: _state.Timer2.SetTarget(value); break;
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case 0xFD: break;
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case 0xFE: break;
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case 0xFF: break;
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}
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}
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uint8_t Spc::CpuReadRegister(uint16_t addr)
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{
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Run();
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return _state.OutputReg[addr & 0x03];
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}
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void Spc::CpuWriteRegister(uint32_t addr, uint8_t value)
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{
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Run();
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_state.CpuRegs[addr & 0x03] = value;
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}
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void Spc::Run()
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{
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int64_t masterClock = _console->GetMemoryManager()->GetMasterClock();
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//TODO: This will overflow after 100+ hours, needs to be fixed
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uint64_t targetCycle = (masterClock * (uint64_t)1024000 / (uint64_t)_console->GetMasterClockRate()) * 2;
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while(_state.Cycle < targetCycle) {
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Exec();
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}
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}
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void Spc::ProcessEndFrame()
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{
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Run();
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int sampleCount = _dsp->sample_count();
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if(sampleCount != 0) {
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_console->GetSoundMixer()->PlayAudioBuffer(_soundBuffer, sampleCount / 2);
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}
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_dsp->set_output(_soundBuffer, Spc::SampleBufferSize >> 1);
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}
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uint8_t* Spc::GetSpcRam()
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{
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return _ram;
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}
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void Spc::Serialize(Serializer &s)
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{
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s.Stream(_state.A, _state.Cycle, _state.PC, _state.PS, _state.SP, _state.X, _state.Y);
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s.Stream(_state.CpuRegs[0], _state.CpuRegs[1], _state.CpuRegs[2], _state.CpuRegs[3]);
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s.Stream(_state.OutputReg[0], _state.OutputReg[1], _state.OutputReg[2], _state.OutputReg[3]);
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s.Stream(_state.RamReg[0], _state.RamReg[1]);
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s.Stream(_state.ExternalSpeed, _state.InternalSpeed, _state.WriteEnabled, _state.TimersEnabled);
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s.Stream(_state.DspReg, _state.RomEnabled);
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_state.Timer0.Serialize(s);
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_state.Timer1.Serialize(s);
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_state.Timer2.Serialize(s);
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ArrayInfo<uint8_t> ram { _ram, Spc::SpcRamSize };
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s.Stream(ram, _state.DspReg, _state.RomEnabled);
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uint8_t dspState[SPC_DSP::state_size];
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memset(dspState, 0, SPC_DSP::state_size);
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if(s.IsSaving()) {
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uint8_t *out = dspState;
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_dsp->copy_state(&out, [](uint8_t** output, void* in, size_t size) {
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memcpy(*output, in, size);
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*output += size;
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});
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s.StreamArray(dspState, SPC_DSP::state_size);
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} else {
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s.StreamArray(dspState, SPC_DSP::state_size);
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uint8_t *in = dspState;
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_dsp->copy_state(&in, [](uint8_t** input, void* output, size_t size) {
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memcpy(output, *input, size);
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*input += size;
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});
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_dsp->set_output(_soundBuffer, Spc::SampleBufferSize >> 1);
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}
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}
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uint8_t Spc::GetOpCode()
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{
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return Read(_state.PC++, MemoryOperationType::ExecOpCode);
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}
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uint8_t Spc::ReadOperandByte()
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{
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return Read(_state.PC++, MemoryOperationType::ExecOperand);
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}
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uint16_t Spc::ReadWord(uint16_t addr, MemoryOperationType type)
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{
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uint8_t lsb = Read(addr, type);
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uint8_t msb = Read(addr + 1, type);
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return (msb << 8) | lsb;
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}
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void Spc::ClearFlags(uint8_t flags)
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{
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_state.PS &= ~flags;
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}
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void Spc::SetFlags(uint8_t flags)
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{
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_state.PS |= flags;
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}
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bool Spc::CheckFlag(uint8_t flag)
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{
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return (_state.PS & flag) == flag;
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}
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void Spc::SetZeroNegativeFlags(uint8_t value)
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{
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ClearFlags(SpcFlags::Zero | SpcFlags::Negative);
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if(value == 0) {
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SetFlags(SpcFlags::Zero);
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} else if(value & 0x80) {
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SetFlags(SpcFlags::Negative);
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}
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}
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void Spc::SetZeroNegativeFlags16(uint16_t value)
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{
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ClearFlags(SpcFlags::Zero | SpcFlags::Negative);
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if(value == 0) {
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SetFlags(SpcFlags::Zero);
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} else if(value & 0x8000) {
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SetFlags(SpcFlags::Negative);
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}
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}
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uint8_t Spc::GetByteValue()
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{
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if(_immediateMode) {
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return (uint8_t)_operandA;
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} else {
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return Read(_operandA);
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}
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}
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uint16_t Spc::GetWordValue()
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{
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if(_immediateMode) {
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return (uint16_t)_operandA;
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} else {
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return ReadWord(_operandA);
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}
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}
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void Spc::Push(uint8_t value)
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{
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Write(0x100 | _state.SP, value);
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_state.SP--;
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}
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uint8_t Spc::Pop()
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{
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_state.SP++;
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return Read(0x100 | _state.SP);
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}
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void Spc::PushWord(uint16_t value)
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{
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Push(value >> 8);
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Push((uint8_t)value);
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}
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uint16_t Spc::PopWord()
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{
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uint8_t lo = Pop();
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uint8_t hi = Pop();
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return lo | hi << 8;
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}
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uint16_t Spc::GetDirectAddress(uint8_t offset)
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{
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return (CheckFlag(SpcFlags::DirectPage) ? 0x100 : 0) + offset;
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}
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