162 lines
3.2 KiB
C++
162 lines
3.2 KiB
C++
#include "stdafx.h"
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#include "Ppu.h"
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#include "Console.h"
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#include "Cpu.h"
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Ppu::Ppu(shared_ptr<Console> console)
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{
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_console = console;
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_vram = new uint8_t[0x10000];
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memset(_vram, 0, 0x10000);
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_layerConfig[0] = {};
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_layerConfig[1] = {};
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_layerConfig[2] = {};
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_layerConfig[3] = {};
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_outputBuffers[0] = new uint16_t[256 * 224];
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_outputBuffers[1] = new uint16_t[256 * 224];
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_currentBuffer = _outputBuffers[0];
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_cgramAddress = 0;
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_vramAddress = 0;
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_vramIncrementValue = 1;
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_vramAddressRemapping = 0;
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_vramAddrIncrementOnSecondReg = false;
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}
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PpuState Ppu::GetState()
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{
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return {
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_cycle,
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_scanline,
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_frameCount
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};
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}
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void Ppu::Exec()
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{
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if(_cycle == 340) {
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_cycle = 0;
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_scanline++;
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if(_scanline == 225) {
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_nmiFlag = true;
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SendFrame();
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if(_enableNmi) {
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_console->GetCpu()->SetNmiFlag();
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}
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}
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if(_scanline == 260) {
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_nmiFlag = false;
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_scanline = 0;
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_frameCount++;
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}
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}
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_cycle++;
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}
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void Ppu::SendFrame()
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{
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for(int i = 0; i < 256 * 224; i++) {
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_currentBuffer[i] = i;
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}
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_currentBuffer = _currentBuffer == _outputBuffers[0] ? _outputBuffers[1] : _outputBuffers[0];
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//_console->GetVideoDecoder()->SendFrame(_currentBuffer);
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}
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uint8_t Ppu::Read(uint16_t addr)
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{
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switch(addr) {
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case 0x4210:
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return _nmiFlag ? 0x80 : 0;
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break;
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case 0x4212:
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return (
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(_scanline >= 225 ? 0x80 : 0) ||
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((_cycle >= 0x121 || _cycle <= 0x15) ? 0x40 : 0)
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);
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break;
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}
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return 0;
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}
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void Ppu::Write(uint32_t addr, uint8_t value)
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{
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switch(addr) {
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case 0x2107: case 0x2108: case 0x2109: case 0x210A:
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//BG 1-4 Tilemap Address and Size (BG1SC, BG2SC, BG3SC, BG4SC)
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_layerConfig[addr - 0x2107].TilemapAddress = (value & 0xFC) << 8;
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_layerConfig[addr - 0x2107].HorizontalMirrorring = (value & 0x01) != 0;
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_layerConfig[addr - 0x2107].VerticalMirrorring = (value & 0x02) != 0;
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break;
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case 0x210B: case 0x210C:
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//BG1+2 / BG3+4 Chr Address (BG12NBA / BG34NBA)
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_layerConfig[addr - 0x210B].ChrAddress = (value & 0x0F) << 12;
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_layerConfig[addr - 0x210B + 1].ChrAddress = (value & 0xF0) << 8;
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break;
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case 0x2115:
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//VMAIN - Video Port Control
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switch(value & 0x03) {
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case 0: _vramIncrementValue = 1; break;
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case 1: _vramIncrementValue = 32; break;
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case 2:
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case 3: _vramIncrementValue = 128; break;
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}
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_vramAddressRemapping = (value & 0x0C) >> 2;
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_vramAddrIncrementOnSecondReg = (value & 0x80) != 0;
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break;
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case 0x2116:
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//VMADDL - VRAM Address low byte
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_vramAddress = (_vramAddress & 0xFF00) | value;
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break;
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case 0x2117:
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//VMADDH - VRAM Address high byte
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_vramAddress = (_vramAddress & 0x00FF) | (value << 8);
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break;
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case 0x2118:
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//VMDATAL - VRAM Data Write low byte
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_vram[_vramAddress << 1] = value;
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if(!_vramAddrIncrementOnSecondReg) {
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_vramAddress += _vramIncrementValue;
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}
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break;
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case 0x2119:
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//VMDATAH - VRAM Data Write high byte
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_vram[(_vramAddress << 1) + 1] = value;
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if(_vramAddrIncrementOnSecondReg) {
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_vramAddress += _vramIncrementValue;
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}
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break;
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case 0x2121:
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//CGRAM Address(CGADD)
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_cgramAddress = value;
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break;
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case 0x2122:
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//CGRAM Data write (CGDATA)
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_cgram[_cgramAddress] = value;
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break;
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case 0x4200:
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_enableNmi = (value & 0x80) != 0;
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break;
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}
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}
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