314 lines
No EOL
8.3 KiB
C++
314 lines
No EOL
8.3 KiB
C++
#pragma once
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#include "stdafx.h"
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#include "Console.h"
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#include "Ppu.h"
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#include "Spc.h"
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#include "RamHandler.h"
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#include "DmaController.h"
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#include "BaseCartridge.h"
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#include "ControlManager.h"
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#include "InternalRegisters.h"
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#include "IMemoryHandler.h"
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#include "MessageManager.h"
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#include "../Utilities/HexUtilities.h"
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class CpuRegisterHandler : public IMemoryHandler
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{
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private:
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Ppu *_ppu;
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Spc *_spc;
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DmaController *_dmaController;
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InternalRegisters *_regs;
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ControlManager *_controlManager;
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uint8_t *_workRam;
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uint32_t _wramPosition;
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public:
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CpuRegisterHandler(Ppu *ppu, Spc *spc, DmaController *dmaController, InternalRegisters *regs, ControlManager *controlManager, uint8_t *workRam)
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{
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_ppu = ppu;
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_spc = spc;
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_regs = regs;
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_dmaController = dmaController;
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_controlManager = controlManager;
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_workRam = workRam;
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_wramPosition = 0;
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}
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uint8_t Read(uint32_t addr) override
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{
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addr &= 0xFFFF;
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if(addr >= 0x2140 && addr <= 0x217F) {
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return _spc->Read(addr & 0x03);
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} else if(addr == 0x2180) {
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return _workRam[_wramPosition++];
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} else if(addr == 0x4016 || addr == 0x4017) {
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return _controlManager->Read(addr);
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} else if(addr < 0x4200) {
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return _ppu->Read(addr);
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} else if(addr >= 0x4300) {
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return _dmaController->Read(addr);
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} else {
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return _regs->Read(addr);
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}
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}
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void Write(uint32_t addr, uint8_t value) override
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{
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addr &= 0xFFFF;
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if(addr >= 0x2140 && addr <= 0x217F) {
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return _spc->Write(addr & 0x03, value);
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} if(addr >= 0x2180 && addr <= 0x2183) {
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switch(addr & 0xFFFF) {
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case 0x2180:
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_workRam[_wramPosition] = value;
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_wramPosition = (_wramPosition + 1) & (0x1FFFF);
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break;
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case 0x2181: _wramPosition = (_wramPosition & 0x1FF00) | value; break;
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case 0x2182: _wramPosition = (_wramPosition & 0x100FF) | (value << 8); break;
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case 0x2183: _wramPosition = (_wramPosition & 0xFFFF) | ((value & 0x01) << 16); break;
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}
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} else if(addr == 0x4016) {
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return _controlManager->Write(addr, value);
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} else if(addr == 0x420B || addr == 0x420C || addr >= 0x4300) {
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_dmaController->Write(addr, value);
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} else if(addr < 0x4200) {
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_ppu->Write(addr, value);
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} else {
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_regs->Write(addr, value);
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}
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}
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};
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class MemoryManager
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{
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public:
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constexpr static uint32_t WorkRamSize = 0x20000;
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private:
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shared_ptr<Console> _console;
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shared_ptr<CpuRegisterHandler> _cpuRegisterHandler;
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InternalRegisters* _regs;
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shared_ptr<Ppu> _ppu;
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IMemoryHandler* _handlers[0x100 * 0x10];
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vector<unique_ptr<RamHandler>> _workRamHandlers;
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uint8_t * _workRam;
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uint64_t _masterClock;
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uint8_t _previousSpeed;
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uint64_t _lastMasterClock;
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uint8_t _masterClockTable[2][0x10000];
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public:
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void Initialize(shared_ptr<Console> console)
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{
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_lastMasterClock = 0;
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_masterClock = 0;
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_console = console;
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_regs = console->GetInternalRegisters().get();
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_ppu = console->GetPpu();
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_workRam = new uint8_t[MemoryManager::WorkRamSize];
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_cpuRegisterHandler.reset(new CpuRegisterHandler(
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_ppu.get(),
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console->GetSpc().get(),
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console->GetDmaController().get(),
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console->GetInternalRegisters().get(),
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console->GetControlManager().get(),
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_workRam
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));
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memset(_handlers, 0, sizeof(_handlers));
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//memset(_workRam, 0, 128 * 1024);
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for(uint32_t i = 0; i < 128 * 1024; i += 0x1000) {
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_workRamHandlers.push_back(unique_ptr<RamHandler>(new RamHandler(_workRam + i)));
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RegisterHandler(0x7E0000 | i, 0x7E0000 | (i + 0xFFF), _workRamHandlers[_workRamHandlers.size() - 1].get());
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}
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for(int i = 0; i <= 0x3F; i++) {
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RegisterHandler((i << 16) | 0x2000, (i << 16) | 0x2FFF, _cpuRegisterHandler.get());
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RegisterHandler(((i | 0x80) << 16) | 0x2000, ((i | 0x80) << 16) | 0x2FFF, _cpuRegisterHandler.get());
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RegisterHandler((i << 16) | 0x4000, (i << 16) | 0x4FFF, _cpuRegisterHandler.get());
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RegisterHandler(((i | 0x80) << 16) | 0x4000, ((i | 0x80) << 16) | 0x4FFF, _cpuRegisterHandler.get());
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}
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for(int i = 0; i < 0x3F; i++) {
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RegisterHandler((i << 16) | 0x0000, (i << 16) | 0x0FFF, _workRamHandlers[0].get());
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RegisterHandler((i << 16) | 0x1000, (i << 16) | 0x1FFF, _workRamHandlers[1].get());
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}
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for(int i = 0x80; i < 0xBF; i++) {
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RegisterHandler((i << 16) | 0x0000, (i << 16) | 0x0FFF, _workRamHandlers[0].get());
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RegisterHandler((i << 16) | 0x1000, (i << 16) | 0x1FFF, _workRamHandlers[1].get());
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}
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console->GetCartridge()->RegisterHandlers(*this);
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GenerateMasterClockTable();
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}
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~MemoryManager()
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{
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delete[] _workRam;
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}
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void RegisterHandler(uint32_t startAddr, uint32_t endAddr, IMemoryHandler* handler)
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{
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if((startAddr & 0xFFF) != 0 || (endAddr & 0xFFF) != 0xFFF) {
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throw std::runtime_error("invalid start/end address");
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}
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for(uint32_t addr = startAddr; addr < endAddr; addr += 0x1000) {
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if(_handlers[addr >> 12]) {
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throw std::runtime_error("handler already set");
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}
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_handlers[addr >> 12] = handler;
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}
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}
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void GenerateMasterClockTable()
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{
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//This is incredibly inaccurate
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for(int j = 0; j < 2; j++) {
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for(int i = 0; i < 0x10000; i++) {
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uint8_t bank = (i & 0xFF00) >> 8;
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if(bank >= 0x40 && bank <= 0x7F) {
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//Slow
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_masterClockTable[j][i] = 8;
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} else if(bank >= 0xCF) {
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//Slow or fast (depending on register)
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_masterClockTable[j][i] = j == 1 ? 6 : 8;
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} else {
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uint8_t page = (i & 0xFF);
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if(page <= 0x1F) {
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//Slow
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_masterClockTable[j][i] = 6;
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} else if(page >= 0x20 && page <= 0x3F) {
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//Fast
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_masterClockTable[j][i] = 6;
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} else if(page == 0x40 || page == 0x41) {
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//Extra slow
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_masterClockTable[j][i] = 12;
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} else if(page >= 0x42 && page <= 0x5F) {
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//Fast
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_masterClockTable[j][i] = 6;
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} else if(page >= 0x60 && page <= 0x7F) {
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//Slow
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_masterClockTable[j][i] = 8;
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} else {
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//page >= $80
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//Slow or fast (depending on register)
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_masterClockTable[j][i] = j == 1 ? 6 : 8;
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}
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}
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}
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}
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}
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void IncrementMasterClock(uint32_t addr)
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{
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_previousSpeed = _masterClockTable[(uint8_t)_regs->IsFastRomEnabled()][addr >> 8];
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_masterClock += _previousSpeed;
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while(_lastMasterClock < _masterClock - 3) {
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_ppu->Exec();
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_lastMasterClock += 4;
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}
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}
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template<uint16_t value>
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void IncrementMasterClockValue()
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{
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_masterClock += value;
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while(_lastMasterClock < _masterClock - 3) {
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_ppu->Exec();
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_lastMasterClock += 4;
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}
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}
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void IncrementMasterClockValue(uint16_t value)
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{
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_masterClock += value;
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while(_lastMasterClock < _masterClock - 3) {
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_ppu->Exec();
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_lastMasterClock += 4;
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}
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}
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uint8_t Read(uint32_t addr, MemoryOperationType type)
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{
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IncrementMasterClock(addr);
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uint8_t value;
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if(_handlers[addr >> 12]) {
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value = _handlers[addr >> 12]->Read(addr);
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} else {
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//open bus
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value = (addr>> 12);
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MessageManager::DisplayMessage("Debug", "Read - missing handler: $" + HexUtilities::ToHex(addr));
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}
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_console->ProcessCpuRead(addr, value, type);
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return value;
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}
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uint8_t ReadDma(uint32_t addr)
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{
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IncrementMasterClockValue<4>();
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uint8_t value;
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if(_handlers[addr >> 12]) {
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value = _handlers[addr >> 12]->Read(addr);
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} else {
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//open bus
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value = (addr >> 12);
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MessageManager::DisplayMessage("Debug", "Read - missing handler: $" + HexUtilities::ToHex(addr));
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}
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_console->ProcessCpuRead(addr, value, MemoryOperationType::DmaRead);
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return value;
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}
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uint8_t Peek(uint32_t addr)
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{
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//Read, without triggering side-effects
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uint8_t value = 0;
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if(_handlers[addr >> 12]) {
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value = _handlers[addr >> 12]->Read(addr);
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}
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return value;
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}
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void Write(uint32_t addr, uint8_t value, MemoryOperationType type)
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{
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IncrementMasterClock(addr);
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_console->ProcessCpuWrite(addr, value, type);
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if(_handlers[addr >> 12]) {
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return _handlers[addr >> 12]->Write(addr, value);
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} else {
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MessageManager::DisplayMessage("Debug", "Write - missing handler: $" + HexUtilities::ToHex(addr) + " = " + HexUtilities::ToHex(value));
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}
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}
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void WriteDma(uint32_t addr, uint8_t value)
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{
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IncrementMasterClockValue<4>();
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_console->ProcessCpuWrite(addr, value, MemoryOperationType::DmaWrite);
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if(_handlers[addr >> 12]) {
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return _handlers[addr >> 12]->Write(addr, value);
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} else {
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MessageManager::DisplayMessage("Debug", "Write - missing handler: $" + HexUtilities::ToHex(addr) + " = " + HexUtilities::ToHex(value));
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}
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}
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uint64_t GetMasterClock() { return _masterClock; }
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uint8_t* DebugGetWorkRam() { return _workRam; }
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}; |