134 lines
No EOL
3.2 KiB
C++
134 lines
No EOL
3.2 KiB
C++
#include "stdafx.h"
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#include "../Utilities/Serializer.h"
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#include "CpuTypes.h"
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#include "Sa1Cpu.h"
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#include "Console.h"
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#include "MemoryManager.h"
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#include "EventType.h"
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#include "Sa1.h"
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#define Cpu Sa1Cpu
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#include "Cpu.Instructions.h"
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#include "Cpu.Shared.h"
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#undef Cpu
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Sa1Cpu::Sa1Cpu(Sa1* sa1, Console* console)
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{
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_sa1 = sa1;
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_console = console;
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}
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Sa1Cpu::~Sa1Cpu()
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{
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}
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void Sa1Cpu::Exec()
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{
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_immediateMode = false;
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switch(_state.StopState) {
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case CpuStopState::Running: RunOp(); break;
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case CpuStopState::Stopped:
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//STP was executed, CPU no longer executes any code
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_state.CycleCount++;
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return;
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case CpuStopState::WaitingForIrq:
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//WAI
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if(!_state.IrqSource && !_state.NmiFlag) {
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Idle();
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} else {
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Idle();
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Idle();
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_state.StopState = CpuStopState::Running;
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}
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break;
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}
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//Use the state of the IRQ/NMI flags on the previous cycle to determine if an IRQ is processed or not
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if(_state.PrevNmiFlag) {
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uint32_t originalPc = GetProgramAddress(_state.PC);
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ProcessInterrupt(_state.EmulationMode ? Sa1Cpu::LegacyNmiVector : Sa1Cpu::NmiVector, true);
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_console->ProcessInterrupt<CpuType::Sa1>(originalPc, GetProgramAddress(_state.PC), true);
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_state.NmiFlag = false;
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} else if(_state.PrevIrqSource) {
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uint32_t originalPc = GetProgramAddress(_state.PC);
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ProcessInterrupt(_state.EmulationMode ? Sa1Cpu::LegacyIrqVector : Sa1Cpu::IrqVector, true);
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_console->ProcessInterrupt<CpuType::Sa1>(originalPc, GetProgramAddress(_state.PC), false);
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}
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}
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void Sa1Cpu::Idle()
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{
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ProcessCpuCycle(0);
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}
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void Sa1Cpu::IdleEndJump()
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{
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if(_sa1->GetSa1MemoryType() == SnesMemoryType::PrgRom) {
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//Jumps/returns in PRG ROM take an extra cycle
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_state.CycleCount++;
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if(IsAccessConflict()) {
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//Add an extra wait cycle if a conflict occurs at the same time
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_state.CycleCount++;
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}
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}
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}
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void Sa1Cpu::IdleTakeBranch()
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{
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if(_sa1->GetSa1MemoryType() == SnesMemoryType::PrgRom && (_state.PC & 0x01)) {
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//Branches to an odd address take an extra cycle
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_state.CycleCount++;
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}
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}
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bool Sa1Cpu::IsAccessConflict()
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{
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return _sa1->GetSnesCpuMemoryType() == _sa1->GetSa1MemoryType() && _sa1->GetSa1MemoryType() != SnesMemoryType::Register;
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}
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void Sa1Cpu::ProcessCpuCycle(uint32_t addr)
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{
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_state.CycleCount++;
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if(_sa1->GetSa1MemoryType() == SnesMemoryType::SaveRam) {
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//BWRAM (save ram) access takes 2 cycles
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_state.CycleCount++;
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if(IsAccessConflict()) {
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_state.CycleCount += 2;
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}
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} else if(IsAccessConflict()) {
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//Add a wait cycle when a conflict occurs between both CPUs
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_state.CycleCount++;
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if(_sa1->GetSa1MemoryType() == SnesMemoryType::Sa1InternalRam) {
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//If it's an IRAM access, add another wait cycle
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_state.CycleCount++;
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}
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}
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_state.PrevNmiFlag = _state.NmiFlag;
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_state.PrevIrqSource = _state.IrqSource && !CheckFlag(ProcFlags::IrqDisable);
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}
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uint8_t Sa1Cpu::Read(uint32_t addr, MemoryOperationType type)
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{
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ProcessCpuCycle(addr);
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return _sa1->ReadSa1(addr, type);
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}
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void Sa1Cpu::Write(uint32_t addr, uint8_t value, MemoryOperationType type)
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{
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ProcessCpuCycle(addr);
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_sa1->WriteSa1(addr, value, type);
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}
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uint16_t Sa1Cpu::GetResetVector()
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{
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return _sa1->ReadSa1(Sa1Cpu::ResetVector) | (_sa1->ReadSa1(Sa1Cpu::ResetVector+1) << 8);
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}
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void Sa1Cpu::IncreaseCycleCount(uint64_t cycleCount)
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{
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_state.CycleCount += cycleCount;
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} |