474 lines
12 KiB
C++
474 lines
12 KiB
C++
#include "stdafx.h"
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#include "MemoryManager.h"
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#include "Console.h"
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#include "BaseCartridge.h"
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#include "Cpu.h"
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#include "Ppu.h"
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#include "DmaController.h"
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#include "RegisterHandlerA.h"
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#include "RegisterHandlerB.h"
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#include "RamHandler.h"
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#include "MessageManager.h"
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#include "DebugTypes.h"
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#include "EmuSettings.h"
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#include "../Utilities/Serializer.h"
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#include "../Utilities/HexUtilities.h"
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void MemoryManager::Initialize(Console *console)
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{
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_masterClock = 0;
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_openBus = 0;
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_cpuSpeed = 8;
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_console = console;
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_regs = console->GetInternalRegisters().get();
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_cpu = console->GetCpu().get();
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_ppu = console->GetPpu().get();
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_workRam = new uint8_t[MemoryManager::WorkRamSize];
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_console->GetSettings()->InitializeRam(_workRam, MemoryManager::WorkRamSize);
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_registerHandlerA.reset(new RegisterHandlerA(
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console->GetDmaController().get(),
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console->GetInternalRegisters().get(),
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console->GetControlManager().get()
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));
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_registerHandlerB.reset(new RegisterHandlerB(
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_console,
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_ppu,
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console->GetSpc().get(),
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_workRam
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));
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memset(_handlers, 0, sizeof(_handlers));
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memset(_hasEvent, 0, sizeof(_hasEvent));
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_hasEvent[276*4] = true;
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_hasEvent[285*4] = true;
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_hasEvent[1360] = true;
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_hasEvent[1364] = true;
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_hasEvent[1368] = true;
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for(uint32_t i = 0; i < 128 * 1024; i += 0x1000) {
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_workRamHandlers.push_back(unique_ptr<RamHandler>(new RamHandler(_workRam, i, MemoryManager::WorkRamSize, SnesMemoryType::WorkRam)));
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}
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RegisterHandler(0x7E, 0x7F, 0x0000, 0xFFFF, _workRamHandlers);
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RegisterHandler(0x00, 0x3F, 0x2000, 0x2FFF, _registerHandlerB.get());
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RegisterHandler(0x80, 0xBF, 0x2000, 0x2FFF, _registerHandlerB.get());
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RegisterHandler(0x00, 0x3F, 0x4000, 0x4FFF, _registerHandlerA.get());
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RegisterHandler(0x80, 0xBF, 0x4000, 0x4FFF, _registerHandlerA.get());
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RegisterHandler(0x00, 0x3F, 0x0000, 0x0FFF, _workRamHandlers[0].get());
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RegisterHandler(0x80, 0xBF, 0x0000, 0x0FFF, _workRamHandlers[0].get());
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RegisterHandler(0x00, 0x3F, 0x1000, 0x1FFF, _workRamHandlers[1].get());
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RegisterHandler(0x80, 0xBF, 0x1000, 0x1FFF, _workRamHandlers[1].get());
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console->GetCartridge()->RegisterHandlers(*this);
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GenerateMasterClockTable();
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UpdateEvents();
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}
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MemoryManager::~MemoryManager()
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{
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delete[] _workRam;
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}
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void MemoryManager::Reset()
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{
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_masterClock = 0;
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_hClock = 0;
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UpdateEvents();
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}
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void MemoryManager::RegisterHandler(uint8_t startBank, uint8_t endBank, uint16_t startPage, uint16_t endPage, vector<unique_ptr<IMemoryHandler>> &handlers, uint16_t pageIncrement, uint16_t startPageNumber)
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{
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if(handlers.empty()) {
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return;
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}
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while(startPageNumber >= handlers.size()) {
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startPageNumber -= (uint32_t)handlers.size();
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}
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uint32_t pageNumber = startPageNumber;
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for(uint32_t i = startBank; i <= endBank; i++) {
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uint32_t baseAddress = i << 16;
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pageNumber += pageIncrement;
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for(uint32_t j = startPage; j <= endPage; j+=0x1000) {
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_handlers[(i << 4) | (j >> 12)] = handlers[pageNumber].get();
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//MessageManager::Log("Map [$" + HexUtilities::ToHex(i) + ":" + HexUtilities::ToHex(j)[1] + "xxx] to page number " + HexUtilities::ToHex(pageNumber));
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pageNumber++;
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if(pageNumber >= handlers.size()) {
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pageNumber = 0;
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}
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}
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}
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}
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void MemoryManager::RegisterHandler(uint8_t startBank, uint8_t endBank, uint16_t startAddr, uint16_t endAddr, IMemoryHandler* handler)
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{
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if((startAddr & 0xFFF) != 0 || (endAddr & 0xFFF) != 0xFFF || startBank > endBank || startAddr > endAddr) {
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throw std::runtime_error("invalid start/end address");
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}
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for(uint32_t bank = startBank; bank <= endBank; bank++) {
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for(uint32_t addr = startAddr; addr < endAddr; addr += 0x1000) {
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/*if(_handlers[addr >> 12]) {
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throw std::runtime_error("handler already set");
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}*/
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_handlers[(bank << 4) | (addr >> 12)] = handler;
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}
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}
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}
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void MemoryManager::GenerateMasterClockTable()
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{
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for(int j = 0; j < 2; j++) {
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for(int i = 0; i < 0x10000; i++) {
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uint8_t bank = (i & 0xFF00) >> 8;
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if(bank >= 0x40 && bank <= 0x7F) {
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//Slow
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_masterClockTable[j][i] = 8;
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} else if(bank >= 0xC0) {
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//Banks $C0-$FF
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//Slow or fast (depending on register)
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_masterClockTable[j][i] = j == 1 ? 6 : 8;
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} else {
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//Banks $00-$3F and $80-$BF
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uint8_t page = (i & 0xFF);
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if(page <= 0x1F) {
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//Slow
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_masterClockTable[j][i] = 8;
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} else if(page >= 0x20 && page <= 0x3F) {
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//Fast
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_masterClockTable[j][i] = 6;
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} else if(page == 0x40 || page == 0x41) {
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//Extra slow
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_masterClockTable[j][i] = 12;
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} else if(page >= 0x42 && page <= 0x5F) {
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//Fast
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_masterClockTable[j][i] = 6;
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} else if(page >= 0x60 && page <= 0x7F) {
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//Slow
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_masterClockTable[j][i] = 8;
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} else if(bank <= 0x3F) {
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//Slow
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_masterClockTable[j][i] = 8;
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} else {
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//page >= $80
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//Slow or fast (depending on register)
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_masterClockTable[j][i] = j == 1 ? 6 : 8;
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}
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}
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}
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}
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}
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void MemoryManager::IncMasterClock4()
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{
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Exec();
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Exec();
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}
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void MemoryManager::IncMasterClock6()
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{
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Exec();
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Exec();
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Exec();
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}
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void MemoryManager::IncMasterClock8()
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{
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Exec();
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Exec();
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Exec();
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Exec();
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}
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void MemoryManager::IncMasterClock40()
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{
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Exec(); Exec(); Exec(); Exec(); Exec();
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Exec(); Exec(); Exec(); Exec(); Exec();
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Exec(); Exec(); Exec(); Exec(); Exec();
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Exec(); Exec(); Exec(); Exec(); Exec();
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}
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void MemoryManager::IncMasterClockStartup()
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{
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for(int i = 0; i < 182 / 2; i++) {
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Exec();
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}
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}
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void MemoryManager::IncrementMasterClockValue(uint16_t cyclesToRun)
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{
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switch(cyclesToRun) {
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case 12: Exec();
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case 10: Exec();
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case 8: Exec();
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case 6: Exec();
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case 4: Exec();
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case 2: Exec();
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}
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}
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void MemoryManager::UpdateEvents()
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{
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_hasEvent[_hdmaInitPosition] = false;
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_hasEvent[_dramRefreshPosition] = false;
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if(_ppu->GetScanline() == 0) {
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_hdmaInitPosition = 12 + (_masterClock & 0x07);
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_hasEvent[_hdmaInitPosition] = true;
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}
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_dramRefreshPosition = 538 - (_masterClock & 0x07);
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_hasEvent[_dramRefreshPosition] = true;
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}
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void MemoryManager::Exec()
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{
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_masterClock += 2;
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_hClock += 2;
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if(_hasEvent[_hClock]) {
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if(_hClock >= 1360 && _ppu->ProcessEndOfScanline(_hClock)) {
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_hClock = 0;
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UpdateEvents();
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}
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if((_hClock & 0x03) == 0) {
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_console->ProcessPpuCycle();
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_regs->ProcessIrqCounters();
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if(_hClock == 276 * 4 && _ppu->GetScanline() < _ppu->GetVblankStart()) {
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_console->GetDmaController()->BeginHdmaTransfer();
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}
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}
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if(_hClock == _hdmaInitPosition && _ppu->GetScanline() == 0) {
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_console->GetDmaController()->BeginHdmaInit();
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}
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if(_hClock == _dramRefreshPosition) {
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IncMasterClock40();
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_cpu->IncreaseCycleCount<5>();
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}
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} else if((_hClock & 0x03) == 0) {
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_console->ProcessPpuCycle();
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_regs->ProcessIrqCounters();
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}
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}
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uint8_t MemoryManager::Read(uint32_t addr, MemoryOperationType type)
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{
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IncrementMasterClockValue(_cpuSpeed - 4);
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uint8_t value;
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if(_handlers[addr >> 12]) {
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value = _handlers[addr >> 12]->Read(addr);
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_openBus = value;
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} else {
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//open bus
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value = _openBus;
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MessageManager::Log("[Debug] Read - missing handler: $" + HexUtilities::ToHex(addr));
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}
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_console->ProcessCpuRead(addr, value, type);
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IncMasterClock4();
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return value;
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}
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uint8_t MemoryManager::ReadDma(uint32_t addr, bool forBusA)
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{
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IncMasterClock4();
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uint8_t value;
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IMemoryHandler* handlers = _handlers[addr >> 12];
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if(handlers) {
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if(forBusA && handlers == _registerHandlerB.get()) {
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//Trying to read from bus B using bus A returns open bus
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value = _openBus;
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} else if(handlers == _registerHandlerA.get()) {
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uint16_t regAddr = addr & 0xFFFF;
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if(regAddr == 0x420B || regAddr == 0x420C || (regAddr >= 0x4300 && regAddr <= 0x437F)) {
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//Trying to read the DMA controller with DMA returns open bus
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value = _openBus;
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} else {
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value = handlers->Read(addr);
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}
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} else {
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value = handlers->Read(addr);
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}
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_openBus = value;
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} else {
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//open bus
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value = _openBus;
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MessageManager::Log("[Debug] Read - missing handler: $" + HexUtilities::ToHex(addr));
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}
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_console->ProcessCpuRead(addr, value, MemoryOperationType::DmaRead);
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return value;
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}
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uint8_t MemoryManager::Peek(uint32_t addr)
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{
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//Read, without triggering side-effects
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uint8_t value = 0;
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if(_handlers[addr >> 12]) {
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value = _handlers[addr >> 12]->Peek(addr);
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}
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return value;
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}
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uint16_t MemoryManager::PeekWord(uint32_t addr)
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{
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uint8_t lsb = Peek(addr);
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uint8_t msb = Peek((addr + 1) & 0xFFFFFF);
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return (msb << 8) | lsb;
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}
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void MemoryManager::PeekBlock(uint32_t addr, uint8_t *dest)
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{
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if(_handlers[addr >> 12]) {
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_handlers[addr >> 12]->PeekBlock(dest);
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} else {
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memset(dest, 0, 0x1000);
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}
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}
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void MemoryManager::Write(uint32_t addr, uint8_t value, MemoryOperationType type)
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{
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IncrementMasterClockValue(_cpuSpeed);
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_console->ProcessCpuWrite(addr, value, type);
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if(_handlers[addr >> 12]) {
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_handlers[addr >> 12]->Write(addr, value);
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} else {
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MessageManager::Log("[Debug] Write - missing handler: $" + HexUtilities::ToHex(addr) + " = " + HexUtilities::ToHex(value));
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}
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}
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void MemoryManager::WriteDma(uint32_t addr, uint8_t value, bool forBusA)
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{
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IncMasterClock4();
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_console->ProcessCpuWrite(addr, value, MemoryOperationType::DmaWrite);
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IMemoryHandler* handlers = _handlers[addr >> 12];
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if(handlers) {
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if(forBusA && handlers == _registerHandlerB.get()) {
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//Trying to write to bus B using bus A does nothing
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} else if(handlers == _registerHandlerA.get()) {
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uint16_t regAddr = addr & 0xFFFF;
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if(regAddr == 0x420B || regAddr == 0x420C || (regAddr >= 0x4300 && regAddr <= 0x437F)) {
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//Trying to write to the DMA controller with DMA does nothing
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} else {
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handlers->Write(addr, value);
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}
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} else {
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handlers->Write(addr, value);
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}
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} else {
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MessageManager::Log("[Debug] Write - missing handler: $" + HexUtilities::ToHex(addr) + " = " + HexUtilities::ToHex(value));
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}
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}
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uint8_t MemoryManager::GetOpenBus()
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{
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return _openBus;
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}
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uint64_t MemoryManager::GetMasterClock()
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{
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return _masterClock;
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}
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uint16_t MemoryManager::GetHClock()
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{
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return _hClock;
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}
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uint8_t * MemoryManager::DebugGetWorkRam()
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{
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return _workRam;
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}
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uint8_t MemoryManager::GetCpuSpeed(uint32_t addr)
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{
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return _masterClockTable[(uint8_t)_regs->IsFastRomEnabled()][addr >> 8];
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}
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uint8_t MemoryManager::GetCpuSpeed()
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{
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return _cpuSpeed;
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}
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void MemoryManager::SetCpuSpeed(uint8_t speed)
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{
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_cpuSpeed = speed;
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}
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bool MemoryManager::IsRegister(uint32_t cpuAddress)
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{
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return _handlers[cpuAddress >> 12] == _registerHandlerA.get() || _handlers[cpuAddress >> 12] == _registerHandlerB.get();
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}
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bool MemoryManager::IsWorkRam(uint32_t cpuAddress)
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{
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IMemoryHandler* handler = _handlers[cpuAddress >> 12];
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return handler && handler->GetMemoryType() == SnesMemoryType::WorkRam;
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}
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AddressInfo MemoryManager::GetAbsoluteAddress(uint32_t addr)
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{
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if(_handlers[addr >> 12]) {
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return _handlers[addr >> 12]->GetAbsoluteAddress(addr);
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} else {
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return { -1, SnesMemoryType::CpuMemory };
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}
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}
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int MemoryManager::GetRelativeAddress(AddressInfo &address, int32_t cpuAddress)
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{
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if(address.Type == SnesMemoryType::WorkRam) {
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return 0x7E0000 | address.Address;
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}
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uint16_t startPosition;
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if(cpuAddress < 0) {
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uint8_t bank = _console->GetCpu()->GetState().K;
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startPosition = ((bank & 0xC0) << 4);
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} else {
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startPosition = (cpuAddress >> 12) & 0xF00;
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}
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for(int i = startPosition; i <= 0xFFF; i++) {
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if(_handlers[i]) {
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AddressInfo addrInfo = _handlers[i]->GetAbsoluteAddress(address.Address & 0xFFF);
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if(addrInfo.Type == address.Type && addrInfo.Address == address.Address) {
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return (i << 12) | (address.Address & 0xFFF);
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}
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}
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}
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for(int i = 0; i < startPosition; i++) {
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if(_handlers[i]) {
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AddressInfo addrInfo = _handlers[i]->GetAbsoluteAddress(address.Address & 0xFFF);
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if(addrInfo.Type == address.Type && addrInfo.Address == address.Address) {
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return (i << 12) | (address.Address & 0xFFF);
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}
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}
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}
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return -1;
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}
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void MemoryManager::Serialize(Serializer &s)
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{
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s.Stream(_masterClock, _openBus, _cpuSpeed, _hClock, _dramRefreshPosition, _hdmaInitPosition);
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s.StreamArray(_workRam, MemoryManager::WorkRamSize);
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s.StreamArray(_hasEvent, sizeof(_hasEvent));
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}
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