62 lines
1.4 KiB
C
62 lines
1.4 KiB
C
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#pragma once
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#include "BaseMapper.h"
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class Waixing178 : public BaseMapper
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{
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private:
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uint8_t _regs[4];
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protected:
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uint16_t GetPRGPageSize() { return 0x4000; }
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uint16_t GetCHRPageSize() { return 0x2000; }
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uint16_t RegisterStartAddress() { return 0x4800; }
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uint16_t RegisterEndAddress() { return 0x4FFF; }
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uint32_t GetWorkRamSize() { return 0x8000; }
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void InitMapper()
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{
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memset(_regs, 0, sizeof(_regs));
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UpdateState();
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SelectCHRPage(0, 0);
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}
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void StreamState(bool saving)
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{
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BaseMapper::StreamState(saving);
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Stream(_regs[0], _regs[1], _regs[2], _regs[3]);
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if(!saving) {
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UpdateState();
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}
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}
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void UpdateState()
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{
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uint16_t sbank = _regs[1] & 0x07;
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uint16_t bbank = _regs[2];
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if(_regs[0] & 0x02) {
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SelectPRGPage(0, (bbank << 3) | sbank);
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if(_regs[0] & 0x04) {
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SelectPRGPage(1, (bbank << 3) | 0x06 | (_regs[1] & 0x01));
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} else {
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SelectPRGPage(1, (bbank << 3) | 0x07);
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}
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} else {
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uint16_t bank = (bbank << 3) | sbank;
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if(_regs[0] & 0x04) {
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SelectPRGPage(0, bank);
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SelectPRGPage(1, bank);
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} else {
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SelectPrgPage2x(0, bank);
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}
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}
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SetCpuMemoryMapping(0x6000, 0x7FFF, _regs[3] & 0x03, PrgMemoryType::WorkRam, MemoryAccessType::ReadWrite);
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SetMirroringType(_regs[0] & 0x01 ? MirroringType::Horizontal : MirroringType::Vertical);
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}
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void WriteRegister(uint16_t addr, uint8_t value)
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{
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_regs[addr & 0x03] = value;
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UpdateState();
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}
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};
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