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PPU: Disabling rendering midscreen should set the vram bus to the value of 'v'

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This prevents jittering in the Steins;Gate 8-bit game that doesn't occur on hardware
This commit is contained in:
Sour 2019-10-12 10:46:08 -04:00
parent 5b6b57be72
commit 30c2c8d3bf
1 changed files with 12 additions and 7 deletions
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19
Core/PPU.cpp
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@ -1260,13 +1260,18 @@ void PPU::UpdateState()
_needStateUpdate = true;
}
if(_prevRenderingEnabled && !_renderingEnabled && _cycle >= 65 && _cycle <= 256 && _scanline < 240) {
//Disabling rendering during OAM evaluation will trigger a glitch causing the current address to be incremented by 1
//The increment can be "delayed" by 1 PPU cycle depending on whether or not rendering is disabled on an even/odd cycle
//e.g, if rendering is disabled on an even cycle, the following PPU cycle will increment the address by 5 (instead of 4)
// if rendering is disabled on an odd cycle, the increment will wait until the next odd cycle (at which point it will be incremented by 1)
//In practice, there is no way to see the difference, so we just increment by 1 at the end of the next cycle after rendering was disabled
_state.SpriteRamAddr++;
if(_prevRenderingEnabled && !_renderingEnabled && _scanline < 240) {
//When rendering is disabled midscreen, set the vram bus back to the value of 'v'
SetBusAddress(_state.VideoRamAddr & 0x3FFF);
if(_cycle >= 65 && _cycle <= 256) {
//Disabling rendering during OAM evaluation will trigger a glitch causing the current address to be incremented by 1
//The increment can be "delayed" by 1 PPU cycle depending on whether or not rendering is disabled on an even/odd cycle
//e.g, if rendering is disabled on an even cycle, the following PPU cycle will increment the address by 5 (instead of 4)
// if rendering is disabled on an odd cycle, the increment will wait until the next odd cycle (at which point it will be incremented by 1)
//In practice, there is no way to see the difference, so we just increment by 1 at the end of the next cycle after rendering was disabled
_state.SpriteRamAddr++;
}
}
if(_updateVramAddrDelay > 0) {