JY Company (Mapper 90, 209, 211) support
This commit is contained in:
Souryo
parent
68c4366cc8
commit
4180b35c84
6 changed files with 431 additions and 6 deletions
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@ -882,8 +882,8 @@ public:
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static void RunDMATransfer(uint8_t* spriteRAM, uint8_t offsetValue);
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static void StartDmcTransfer();
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static uint32_t GetClockRate(NesModel model);
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static bool IsCpuWrite() { return CPU::Instance->_cpuWrite; }
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//Used by debugger for "Set Next Statement"
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void SetDebugPC(uint16_t value) { SetPC(value); _state.DebugPC = value; }
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@ -439,6 +439,7 @@
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<ClInclude Include="JalecoJf13.h" />
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<ClInclude Include="JalecoJf16.h" />
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<ClInclude Include="JalecoJf17_19.h" />
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<ClInclude Include="JyCompany.h" />
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<ClInclude Include="Kaiser202.h" />
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<ClInclude Include="Kaiser7022.h" />
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<ClInclude Include="Kaiser7058.h" />
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@ -778,6 +778,9 @@
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<ClInclude Include="Bmc63.h">
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<Filter>Nes\Mappers</Filter>
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</ClInclude>
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<ClInclude Include="JyCompany.h">
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<Filter>Nes\Mappers</Filter>
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</ClInclude>
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</ItemGroup>
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<ItemGroup>
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<ClCompile Include="stdafx.cpp">
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403
Core/JyCompany.h
Normal file
403
Core/JyCompany.h
Normal file
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@ -0,0 +1,403 @@
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#pragma once
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#include "stdafx.h"
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#include "BaseMapper.h"
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#include "CPU.h"
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class JyCompany : public BaseMapper
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{
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private:
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enum class JyIrqSource
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{
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CpuClock = 0,
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PpuA12Rise = 1,
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PpuRead = 2,
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CpuWrite = 3
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};
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uint8_t _prgRegs[4];
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uint8_t _chrLowRegs[8];
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uint8_t _chrHighRegs[8];
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uint8_t _chrLatch[2];
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uint8_t _prgMode;
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bool _enablePrgAt6000;
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uint8_t _chrMode;
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bool _chrBlockMode;
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uint8_t _chrBlock;
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bool _mirrorChr;
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uint8_t _mirroringReg;
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bool _advancedNtControl;
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bool _disableNtRam;
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uint8_t _ntRamSelectBit;
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uint8_t _ntLowRegs[4];
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uint8_t _ntHighRegs[4];
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bool _irqEnabled;
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JyIrqSource _irqSource;
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uint8_t _irqCountDirection;
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bool _irqFunkyMode;
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uint8_t _irqFunkyModeReg;
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bool _irqSmallPrescaler;
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uint8_t _irqPrescaler;
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uint8_t _irqCounter;
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uint8_t _irqXorReg;
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uint8_t _multiplyValue1;
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uint8_t _multiplyValue2;
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uint8_t _regRamValue;
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uint16_t _lastPpuAddr;
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protected:
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virtual uint16_t GetPRGPageSize() { return 0x2000; }
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virtual uint16_t GetCHRPageSize() { return 0x0400; }
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virtual bool AllowRegisterRead() { return true; }
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void InitMapper()
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{
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RemoveRegisterRange(0x8000, 0xFFFF, MemoryOperation::Read);
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AddRegisterRange(0x5000, 0x5FFF, MemoryOperation::Any);
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_chrLatch[0] = 0;
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_chrLatch[1] = 4;
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memset(_prgRegs, 0, sizeof(_prgRegs));
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memset(_chrLowRegs, 0, sizeof(_chrLowRegs));
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memset(_chrHighRegs, 0, sizeof(_chrHighRegs));
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_prgMode = 0;
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_enablePrgAt6000 = false;
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_chrMode = 0;
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_chrBlockMode = false;
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_chrBlock = 0;
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_mirrorChr = false;
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_mirroringReg = 0;
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_advancedNtControl = false;
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_disableNtRam = false;
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_ntRamSelectBit = 0;
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memset(_ntLowRegs, 0, sizeof(_ntLowRegs));
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memset(_ntHighRegs, 0, sizeof(_ntHighRegs));
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_irqEnabled = false;
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_irqSource = JyIrqSource::CpuClock;
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_lastPpuAddr = 0;
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_irqCountDirection = 0;
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_irqFunkyMode = false;
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_irqFunkyModeReg = 0;
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_irqSmallPrescaler = false;
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_irqPrescaler = 0;
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_irqCounter = 0;
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_irqXorReg = 0;
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_multiplyValue1 = 0;
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_multiplyValue2 = 0;
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_regRamValue = 0;
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UpdateState();
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}
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void StreamState(bool saving)
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{
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BaseMapper::StreamState(saving);
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ArrayInfo<uint8_t> prgRegs{ _prgRegs, 4 };
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ArrayInfo<uint8_t> chrLowRegs{ _chrLowRegs, 8 };
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ArrayInfo<uint8_t> chrHighRegs{ _chrHighRegs, 8 };
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ArrayInfo<uint8_t> ntLowRegs{ _ntLowRegs, 4 };
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ArrayInfo<uint8_t> ntHighRegs{ _ntHighRegs, 4 };
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Stream(_chrLatch[0], _chrLatch[1], _prgMode, _enablePrgAt6000, _chrMode, _chrBlockMode, _chrBlock, _mirrorChr, _mirroringReg, _advancedNtControl,
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_disableNtRam, _ntRamSelectBit, _irqEnabled, _irqSource, _lastPpuAddr, _irqCountDirection, _irqFunkyMode, _irqFunkyModeReg, _irqSmallPrescaler,
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_irqPrescaler, _irqCounter, _irqXorReg, _multiplyValue1, _multiplyValue2, _regRamValue, prgRegs, chrLowRegs, chrHighRegs, ntLowRegs, ntHighRegs);
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if(!saving) {
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UpdateState();
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}
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}
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void UpdateState()
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{
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UpdatePrgState();
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UpdateChrState();
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UpdateMirroringState();
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}
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uint8_t InvertPrgBits(uint8_t prgReg, bool needInvert)
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{
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if(needInvert) {
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return (prgReg & 0x01) << 6 | (prgReg & 0x02) << 4 | (prgReg & 0x04) << 2 | (prgReg & 0x10) >> 2 | (prgReg & 0x20) >> 4 | (prgReg & 0x40) >> 6;
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} else {
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return prgReg;
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}
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}
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void UpdatePrgState()
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{
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bool invertBits = (_prgMode & 0x03) == 0x03;
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int prgRegs[4] = { InvertPrgBits(_prgRegs[0], invertBits), InvertPrgBits(_prgRegs[1], invertBits),
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InvertPrgBits(_prgRegs[2], invertBits), InvertPrgBits(_prgRegs[3], invertBits) };
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int lastPage = (_prgMode & 0x04) ? prgRegs[3] : -1;
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switch(_prgMode & 0x03) {
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case 0:
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SelectPrgPage4x(0, lastPage * 4);
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if(_enablePrgAt6000) {
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SetCpuMemoryMapping(0x6000, 0x7FFF, prgRegs[3] * 4 + 3, PrgMemoryType::PrgRom);
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}
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break;
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case 1:
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SelectPrgPage2x(0, prgRegs[1] << 1);
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SelectPrgPage2x(1, lastPage * 2);
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if(_enablePrgAt6000) {
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SetCpuMemoryMapping(0x6000, 0x7FFF, prgRegs[3] * 2 + 1, PrgMemoryType::PrgRom);
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}
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break;
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case 2:
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case 3:
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SelectPRGPage(0, prgRegs[0]);
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SelectPRGPage(1, prgRegs[1]);
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SelectPRGPage(2, prgRegs[2]);
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SelectPRGPage(3, lastPage);
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if(_enablePrgAt6000) {
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SetCpuMemoryMapping(0x6000, 0x7FFF, prgRegs[3], PrgMemoryType::PrgRom);
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}
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break;
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}
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if(!_enablePrgAt6000) {
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RemoveCpuMemoryMapping(0x6000, 0x7FFF);
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}
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}
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uint16_t GetChrReg(int index)
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{
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if(_chrMode >= 2 && _mirrorChr && (index == 2 || index == 3)) {
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index -= 2;
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}
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if(_chrBlockMode) {
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return _chrLowRegs[index] | (_chrBlock << 8);
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} else {
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return _chrLowRegs[index] | (_chrHighRegs[index] << 8);
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}
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}
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void UpdateChrState()
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{
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int chrRegs[8] = { GetChrReg(0), GetChrReg(1), GetChrReg(2), GetChrReg(3), GetChrReg(4), GetChrReg(5), GetChrReg(6), GetChrReg(7) };
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switch(_chrMode) {
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case 0:
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SelectChrPage8x(0, chrRegs[0] << 3);
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break;
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case 1:
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SelectChrPage4x(0, chrRegs[_chrLatch[0]] << 2);
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SelectChrPage4x(1, chrRegs[_chrLatch[1]] << 2);
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break;
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case 2:
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SelectChrPage2x(0, chrRegs[0] << 1);
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SelectChrPage2x(1, chrRegs[2] << 1);
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SelectChrPage2x(2, chrRegs[4] << 1);
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SelectChrPage2x(3, chrRegs[6] << 1);
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break;
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case 3:
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for(int i = 0; i < 8; i++) {
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SelectCHRPage(i, chrRegs[i]);
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}
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break;
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}
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}
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void UpdateMirroringState()
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{
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//"Mapper 211 behaves as though N were always set (1), and mapper 090 behaves as though N were always clear(0)."
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if((_advancedNtControl || _mapperID == 211) && _mapperID != 90) {
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for(int i = 0; i < 4; i++) {
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if(_disableNtRam || (_ntLowRegs[i] & 0x80) != (_ntRamSelectBit & 0x80)) {
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SetPpuMemoryMapping(0x2000 + 0x400 * i, 0x23FF + 0x400 * i, _ntLowRegs[i] | (_ntHighRegs[i] << 8), ChrMemoryType::ChrRom);
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} else {
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SetNametable(i, _ntLowRegs[i] & 0x01);
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}
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}
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} else {
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switch(_mirroringReg) {
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case 0: SetMirroringType(MirroringType::Vertical); break;
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case 1: SetMirroringType(MirroringType::Horizontal); break;
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case 2: SetMirroringType(MirroringType::ScreenAOnly); break;
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case 3: SetMirroringType(MirroringType::ScreenBOnly); break;
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}
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}
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}
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uint8_t ReadRegister(uint16_t addr)
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{
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switch(addr & 0xF803) {
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case 0x5000: return 0; //Dip switches
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case 0x5800: return (_multiplyValue1 * _multiplyValue2) & 0xFF;
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case 0x5801: return ((_multiplyValue1 * _multiplyValue2) >> 8) & 0xFF;
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case 0x5803: return _regRamValue;
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}
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return MemoryManager::GetOpenBus();
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}
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void WriteRegister(uint16_t addr, uint8_t value)
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{
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if(addr < 0x8000) {
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switch(addr & 0xF803) {
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case 0x5800: _multiplyValue1 = value; break;
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case 0x5801: _multiplyValue2 = value; break;
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case 0x5803: _regRamValue = value; break;
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}
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} else {
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switch(addr & 0xF007) {
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case 0x8000: case 0x8001: case 0x8002: case 0x8003:
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case 0x8004: case 0x8005: case 0x8006: case 0x8007:
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_prgRegs[addr & 0x03] = value & 0x7F;
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break;
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case 0x9000: case 0x9001: case 0x9002: case 0x9003:
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case 0x9004: case 0x9005: case 0x9006: case 0x9007:
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_chrLowRegs[addr & 0x07] = value;
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break;
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case 0xA000: case 0xA001: case 0xA002: case 0xA003:
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case 0xA004: case 0xA005: case 0xA006: case 0xA007:
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_chrHighRegs[addr & 0x07] = value;
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break;
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case 0xB000: case 0xB001: case 0xB002: case 0xB003:
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_ntLowRegs[addr & 0x03] = value;
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break;
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case 0xB004: case 0xB005: case 0xB006: case 0xB007:
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_ntHighRegs[addr & 0x03] = value;
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break;
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case 0xC000:
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if(value & 0x01) {
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_irqEnabled = true;
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} else {
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_irqEnabled = false;
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CPU::ClearIRQSource(IRQSource::External);
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}
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break;
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case 0xC001:
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_irqCountDirection = (value >> 6) & 0x03;
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_irqFunkyMode = (value & 0x08) == 0x08;
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_irqSmallPrescaler = ((value >> 2) & 0x01) == 0x01;
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_irqSource = (JyIrqSource)(value & 0x03);
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break;
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case 0xC002:
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_irqEnabled = false;
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CPU::ClearIRQSource(IRQSource::External);
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break;
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case 0xC003: _irqEnabled = true; break;
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case 0xC004: _irqPrescaler = value ^ _irqXorReg; break;
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case 0xC005: _irqCounter = value ^ _irqXorReg; break;
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case 0xC006: _irqXorReg = value; break;
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case 0xC007: _irqFunkyModeReg = value; break;
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case 0xD000:
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_prgMode = value & 0x07;
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_chrMode = (value >> 3) & 0x03;
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_advancedNtControl = (value & 0x20) == 0x20;
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_disableNtRam = (value & 0x40) == 0x40;
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_enablePrgAt6000 = (value & 0x80) == 0x80;
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break;
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case 0xD001: _mirroringReg = value & 0x03; break;
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case 0xD002: _ntRamSelectBit = value & 0x80; break;
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case 0xD003:
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_mirrorChr = (value & 0x80) == 0x80;
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_chrBlockMode = (value & 0x20) == 0x00;
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_chrBlock = value & 0x1F;
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break;
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}
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}
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UpdateState();
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}
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void ProcessCpuClock()
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{
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if(_irqSource == JyIrqSource::CpuClock || (_irqSource == JyIrqSource::CpuWrite && CPU::IsCpuWrite())) {
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TickIrqCounter();
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}
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}
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uint8_t ReadVRAM(uint16_t addr, MemoryOperationType type)
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{
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if(_irqSource == JyIrqSource::PpuRead && type == MemoryOperationType::PpuRenderingRead) {
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TickIrqCounter();
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}
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return BaseMapper::ReadVRAM(addr, type);
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}
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void NotifyVRAMAddressChange(uint16_t addr)
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{
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if(_irqSource == JyIrqSource::PpuA12Rise && (addr & 0x1000) && !(_lastPpuAddr & 0x1000)) {
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TickIrqCounter();
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}
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_lastPpuAddr = addr;
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if(_mapperID == 209) {
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switch(addr & 0x2FF8) {
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case 0x0FD8:
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case 0x0FE8:
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_chrLatch[addr >> 12] = addr >> 4 & ((addr >> 10 & 0x04) | 0x02);
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UpdateChrState();
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break;
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}
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}
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}
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void TickIrqCounter()
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{
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bool clockIrqCounter = false;
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uint8_t mask = _irqSmallPrescaler ? 0x07 : 0xFF;
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uint8_t prescaler = _irqPrescaler & mask;
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if(_irqCountDirection == 0x01) {
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prescaler++;
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if((prescaler & mask) == 0) {
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clockIrqCounter = true;
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}
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} else if(_irqCountDirection == 0x02) {
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if(--prescaler == 0) {
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clockIrqCounter = true;
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}
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}
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_irqPrescaler = (_irqPrescaler & ~mask) | (prescaler & mask);
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if(clockIrqCounter) {
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if(_irqCountDirection == 0x01) {
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_irqCounter++;
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if(_irqCounter == 0 && _irqEnabled) {
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CPU::SetIRQSource(IRQSource::External);
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}
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} else if(_irqCountDirection == 0x02) {
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_irqCounter--;
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if(_irqCounter == 0xFF && _irqEnabled) {
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CPU::SetIRQSource(IRQSource::External);
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}
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}
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}
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}
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};
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@ -34,6 +34,7 @@
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#include "JalecoJf17_19.h"
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#include "JalecoJfxx.h"
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#include "JalecoSs88006.h"
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#include "JyCompany.h"
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#include "Kaiser202.h"
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#include "Kaiser7022.h"
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#include "Kaiser7058.h"
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@ -135,14 +136,17 @@
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#include "Waixing252.h"
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/*
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Supported mappers: (... denotes bad mappers, --- denotes potentially bad mappers)
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Supported mappers:
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... : bad mappers
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--- : potentially bad mappers
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=== : not supported by Nestopia & FCEUX
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-----------------------------------------------------------------
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| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10| 11| 12| 13| | 15|
|
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| 16| 17| 18| 19|...| 21| 22| 23| 24| 25| 26| 27| 28| | | 31|
|
||||
| 32| 33| 34| | 36| 37| 38|---| 40| 41| 42|---| 44| 45| 46| 47|
|
||||
| 48| 49| 50| 51| 52| | | | 56| 57| 58| | 60| 61| 62| 63|
|
||||
| 48| 49| 50| 51| 52| | | | 56| 57| 58|===| 60| 61| 62| 63|
|
||||
| 64| 65| 66| 67| 68| 69| 70| 71| 72| 73| 74| 75| 76| 77| 78| 79|
|
||||
| 80| | 82| | | 85| 86| 87| 88| 89| | 91| 92| 93| 94| 95|
|
||||
| 80|===| 82| |===| 85| 86| 87| 88| 89| 90| 91| 92| 93| 94| 95|
|
||||
| | 97| | 99|...|101| | | | | |107| | | | |
|
||||
|112|113| |115| | |118|119| | | | | | | | |
|
||||
| | | | |132|133| | | |137|138|139|140|141|142|143|
|
||||
|
|
@ -150,7 +154,7 @@ Supported mappers: (... denotes bad mappers, --- denotes potentially bad mapper
|
|||
| | | |163|164| | | | | |170|171|172|173| |175|
|
||||
|176|177| |179|180| |182| |184|185| | | |189| |191|
|
||||
|192|193|194|195| | | | |200|201|202|203| |205|206|207|
|
||||
| | |210| | | | | | | |218| | | | | |
|
||||
| |209|210|211| | | | | | |218| | | | | |
|
||||
| |225|226|227|228| |230|231|232| | |235| | | | |
|
||||
|240|241|242|243| | |246| | | | | |252| | | |
|
||||
-----------------------------------------------------------------
|
||||
|
|
@ -247,6 +251,7 @@ BaseMapper* MapperFactory::GetMapperFromID(RomData &romData)
|
|||
case 87: return new JalecoJfxx(false);
|
||||
case 88: return new Namco108_88();
|
||||
case 89: return new Sunsoft89();
|
||||
case 90: return new JyCompany();
|
||||
case 91: return new Mapper91();
|
||||
case 92: return new JalecoJf17_19(true);
|
||||
case 93: return new Sunsoft93();
|
||||
|
|
@ -314,7 +319,9 @@ BaseMapper* MapperFactory::GetMapperFromID(RomData &romData)
|
|||
case 205: return new MMC3_205();
|
||||
case 206: return new Namco108();
|
||||
case 207: return new TaitoX1005(true);
|
||||
case 209: return new JyCompany();
|
||||
case 210: return new Namco163();
|
||||
case 211: return new JyCompany();
|
||||
case 218: return new Mapper218();
|
||||
case 225: return new Mapper225();
|
||||
case 226: return new Mapper226();
|
||||
|
|
|
|||
11
Core/PPU.cpp
11
Core/PPU.cpp
|
|
@ -670,6 +670,9 @@ void PPU::ProcessPreVBlankScanline()
|
|||
if(_cycle == 257) {
|
||||
_spriteIndex = 0;
|
||||
}
|
||||
} else if((_cycle - 259) % 8 == 0) {
|
||||
//Garbage AT sprite fetch
|
||||
_memoryManager->ReadVRAM(GetAttributeAddr());
|
||||
}
|
||||
}
|
||||
} else if(_cycle == 321 && IsRenderingEnabled()) {
|
||||
|
|
@ -709,6 +712,10 @@ void PPU::ProcessPrerenderScanline()
|
|||
_scanline = 0;
|
||||
} else if(_cycle >= 321 && _cycle <= 336) {
|
||||
LoadTileInfo();
|
||||
} else if(_cycle == 337 || _cycle == 339) {
|
||||
if(IsRenderingEnabled()) {
|
||||
_memoryManager->ReadVRAM(GetNameTableAddr());
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -725,6 +732,10 @@ void PPU::ProcessVisibleScanline()
|
|||
}
|
||||
} else if(_cycle >= 321 && _cycle <= 336) {
|
||||
LoadTileInfo();
|
||||
} else if(_cycle == 337 || _cycle == 339) {
|
||||
if(IsRenderingEnabled()) {
|
||||
_memoryManager->ReadVRAM(GetNameTableAddr());
|
||||
}
|
||||
}
|
||||
|
||||
ProcessPreVBlankScanline();
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue