From ad085f1a759ac938e3ec169b363bcc48c4d34fe3 Mon Sep 17 00:00:00 2001
From: Souryo <mesenemu@gmail.com>
Date: Tue, 18 Aug 2015 18:02:40 -0400
Subject: [PATCH] MMC5 - Fixed a few bugs

---
 Core/BaseMapper.h |  8 ++++++++
 Core/MMC5.h       | 16 ++++++++++------
 2 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/Core/BaseMapper.h b/Core/BaseMapper.h
index 473f7dd1..46340296 100644
--- a/Core/BaseMapper.h
+++ b/Core/BaseMapper.h
@@ -410,6 +410,8 @@ class BaseMapper : public IMemoryHandler, public Snapshotable, public INotificat
 				return ReadRegister(addr);
 			} else if(_prgPageAccessType[addr >> 8] & MemoryAccessType::Read) {
 				return _prgPages[addr >> 8][addr & 0xFF];
+			} else {
+				//assert(false);
 			}
 			return 0;
 		}
@@ -420,6 +422,8 @@ class BaseMapper : public IMemoryHandler, public Snapshotable, public INotificat
 				WriteRegister(addr, value);
 			} else if(_prgPageAccessType[addr >> 8] & MemoryAccessType::Write) {
 				_prgPages[addr >> 8][addr & 0xFF] = value;
+			} else {
+				//assert(false);
 			}
 		}
 		
@@ -427,6 +431,8 @@ class BaseMapper : public IMemoryHandler, public Snapshotable, public INotificat
 		{
 			if(_chrPageAccessType[addr >> 8] & MemoryAccessType::Read) {
 				return _chrPages[addr >> 8][addr & 0xFF];
+			} else {
+				//assert(false);
 			}
 			return 0;
 		}
@@ -435,6 +441,8 @@ class BaseMapper : public IMemoryHandler, public Snapshotable, public INotificat
 		{
 			if(_chrPageAccessType[addr >> 8] & MemoryAccessType::Write) {
 				_chrPages[addr >> 8][addr & 0xFF] = value;
+			} else {
+				//assert(false);
 			}
 		}
 
diff --git a/Core/MMC5.h b/Core/MMC5.h
index e40c56f3..8aa09c75 100644
--- a/Core/MMC5.h
+++ b/Core/MMC5.h
@@ -64,8 +64,8 @@ private:
 		if((((bankNumber & 0x80) == 0x00) && reg != 0x04) || reg == 0x00) {
 			bankNumber &= 0x07;
 			memoryType = PrgMemoryType::SaveRam;
-			uint8_t accessType = MemoryAccessType::Read;
-			if(_prgRamProtect1 == 0x10 && _prgRamProtect2 == 0x01) {
+			accessType = MemoryAccessType::Read;
+			if(_prgRamProtect1 == 0x02 && _prgRamProtect2 == 0x01) {
 				accessType |= MemoryAccessType::Write;
 			}
 		} else {
@@ -246,7 +246,7 @@ private:
 protected:
 	virtual uint16_t GetPRGPageSize() { return 0x2000; }
 	virtual uint16_t GetCHRPageSize() {	return 0x400; }
-	virtual uint16_t RegisterStartAddress() { return 0x5100; }
+	virtual uint16_t RegisterStartAddress() { return 0x5000; }
 	virtual uint16_t RegisterEndAddress() { return 0x5206; }
 	virtual uint32_t GetSaveRamSize() { return 0x10000; } //Emulate as if a single 64k block of saved ram existed
 	virtual uint32_t GetSaveRamPageSize() { return 0x2000; }
@@ -312,9 +312,13 @@ protected:
 
 	virtual void WriteRAM(uint16_t addr, uint8_t value)
 	{
-		if(_ppuInFrame && addr >= 0x5C00 && addr <= 0x5FFF && _extendedRamMode <= 1) {
-			//Mode 0/1 - Not readable (returns open bus), can only be written while the PPU is rendering (otherwise, 0 is written)
-			value = 0;
+		if(addr >= 0x5C00 && addr <= 0x5FFF && _extendedRamMode <= 1) {
+			PPUControlFlags flags = PPU::GetControlFlags();
+			if(!flags.BackgroundEnabled && !flags.SpritesEnabled) {
+				//Expansion RAM ($5C00-$5FFF, read/write)
+				//Mode 0/1 - Not readable (returns open bus), can only be written while the PPU is rendering (otherwise, 0 is written)
+				value = 0;
+			}
 		}
 		BaseMapper::WriteRAM(addr, value);
 	}