UNIF: Added support for UNL-DRIPGAME boards
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Sour
parent
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commit
cef7fa9eaa
7 changed files with 320 additions and 4 deletions
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@ -903,6 +903,8 @@
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<ClInclude Include="UnifLoader.h" />
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<ClInclude Include="Unl255in1.h" />
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<ClInclude Include="Unl43272.h" />
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<ClInclude Include="UnlDripGame.h" />
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<ClInclude Include="UnlDripGameAudio.h" />
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<ClInclude Include="UnlPuzzle.h" />
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<ClInclude Include="UnlVrc7.h" />
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<ClInclude Include="UnRom512.h" />
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@ -1432,6 +1432,12 @@
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<ClInclude Include="BmcGn45.h">
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<Filter>Nes\Mappers\Unif</Filter>
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</ClInclude>
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<ClInclude Include="UnlDripGame.h">
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<Filter>Nes\Mappers\Unif</Filter>
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</ClInclude>
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<ClInclude Include="UnlDripGameAudio.h">
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<Filter>Nes\Mappers\Unif</Filter>
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</ClInclude>
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</ItemGroup>
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<ItemGroup>
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<ClCompile Include="stdafx.cpp">
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@ -244,6 +244,7 @@
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#include "Unl43272.h"
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#include "Unl8237A.h"
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#include "UnlD1038.h"
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#include "UnlDripGame.h"
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#include "UnlPci556.h"
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#include "UnlPuzzle.h"
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#include "UnlVrc7.h"
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@ -273,18 +274,18 @@ Supported mappers:
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-----------------------------------------------------------------
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| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10| 11| 12| 13| 14| 15|
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| 16| 17| 18| 19|...| 21| 22| 23| 24| 25| 26| 27| 28| 29| 30| 31|
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| 32| 33| 34| 35| 36| 37| 38|---| 40| 41| 42| 43| 44| 45| 46| 47|
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| 32| 33| 34| 35| 36| 37| 38| 39| 40| 41| 42| 43| 44| 45| 46| 47|
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| 48| 49| 50| 51| 52| 53| 54|???| 56| 57| 58|===| 60| 61| 62| 63|
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| 64| 65| 66| 67| 68| 69| 70| 71| 72| 73| 74| 75| 76| 77| 78| 79|
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| 80|===| 82| 83|===| 85| 86| 87| 88| 89| 90| 91| 92| 93| 94| 95|
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| 96| 97|===| 99|...|101|===|103|104|105|106|107|108|===|===|111|
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|112|113|114|115| |117|118|119|120|121|===|123|===|125|126|===|
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|112|113|114|115|116|117|118|119|120|121|===|123|===|125|126|===|
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|===|===|===|===|132|133|134|===|136|137|138|139|140|141|142|143|
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|144|145|146|147|148|149|150|151|152|153|154|155|156|157|158|159|
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|---|===|162|163|164|165|166|167|168|===|170|171|172|173|174|175|
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|176|177|178|179|180|---|182|183|184|185|186|187|188|189|190|191|
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|192|193|194|195|196|197| |199|200|201|202|203|204|205|206|207|
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|???|209|210|211|212|213|214|215|216|217|218|219|220|221|222|???|
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|192|193|194|195|196|197|198|199|200|201|202|203|204|205|206|207|
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|208|209|210|211|212|213|214|215|216|217|218|219|220|221|222|???|
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|???|225|226|227|228|229|230|231|232|233|234|235|236|===|238|===|
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|240|241|242|243|244|245|246|===|===|249|250|===|252|253|254|255|
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-----------------------------------------------------------------
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@ -592,6 +593,7 @@ BaseMapper* MapperFactory::GetMapperFromID(RomData &romData)
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case UnifBoards::Unl43272: return new Unl43272();
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case UnifBoards::Unl8237A: return new Unl8237A();
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case UnifBoards::UnlD1038: return new UnlD1038();
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case UnifBoards::UnlDripGame: return new UnlDripGame();
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case UnifBoards::UnlPuzzle: return new UnlPuzzle();
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case UnifBoards::UnlVrc7: return new UnlVrc7();
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case UnifBoards::Yoko: return new Yoko();
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@ -70,5 +70,6 @@ namespace UnifBoards {
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BmcHpxx,
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DragonFighter,
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BmcGn45,
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UnlDripGame,
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};
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}
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@ -160,4 +160,5 @@ std::unordered_map<string, int> UnifLoader::_boardMappings = std::unordered_map<
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{ "WAIXING-FS005", UnifBoards::UnknownBoard },
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{ "HPxx", UnifBoards::BmcHpxx },
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{ "GN-45", UnifBoards::BmcGn45 }, //Doesn't actually exist as a UNIF file (used to assign a mapper to GN-45 boards)
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{ "DRIPGAME", UnifBoards::UnlDripGame },
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};
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169
Core/UnlDripGame.h
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169
Core/UnlDripGame.h
Normal file
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@ -0,0 +1,169 @@
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#pragma once
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#include "stdafx.h"
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#include "BaseMapper.h"
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#include "UnlDripGameAudio.h"
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class UnlDripGame : public BaseMapper
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{
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private:
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UnlDripGameAudio _audioChannels[2];
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uint8_t _extendedAttributes[2][0x400];
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uint8_t _lowByteIrqCounter;
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uint16_t _irqCounter;
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uint16_t _lastNametableFetchAddr;
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bool _irqEnabled;
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bool _extAttributesEnabled;
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bool _wramWriteEnabled;
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bool _dipSwitch;
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protected:
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uint16_t GetPRGPageSize() override { return 0x4000; }
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uint16_t GetCHRPageSize() override { return 0x800; }
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bool AllowRegisterRead() override { return true; }
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uint16_t RegisterStartAddress() override { return 0x8000; }
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uint16_t RegisterEndAddress() override { return 0xFFFF; }
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void InitMapper() override
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{
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_lowByteIrqCounter = 0;
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_irqCounter = 0;
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_irqEnabled = false;
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_extAttributesEnabled = false;
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_wramWriteEnabled = false;
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_dipSwitch = false;
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_lastNametableFetchAddr = 0;
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InitializeRam(_extendedAttributes[0], 0x400);
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InitializeRam(_extendedAttributes[1], 0x400);
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SelectPRGPage(1, -1);
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AddRegisterRange(0x4800, 0x5FFF, MemoryOperation::Read);
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RemoveRegisterRange(0x8000, 0xFFFF, MemoryOperation::Read);
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}
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void StreamState(bool saving) override
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{
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BaseMapper::StreamState(saving);
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ArrayInfo<uint8_t> extAttributes1 { _extendedAttributes[0], 0x400 };
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ArrayInfo<uint8_t> extAttributes2 { _extendedAttributes[1], 0x400 };
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SnapshotInfo audioChannel1 { &_audioChannels[0] };
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SnapshotInfo audioChannel2 { &_audioChannels[1] };
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Stream(extAttributes1, extAttributes2, audioChannel1, audioChannel2, _lowByteIrqCounter, _irqCounter, _irqEnabled,
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_extAttributesEnabled, _wramWriteEnabled, _dipSwitch);
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if(!saving) {
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UpdateWorkRamState();
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}
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}
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void ProcessCpuClock() override
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{
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if(_irqEnabled) {
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if(_irqCounter > 0) {
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_irqCounter--;
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if(_irqCounter == 0) {
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//While the IRQ counter is enabled, the timer is decremented once per CPU
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//cycle.Once the timer reaches zero, the /IRQ line is set to logic 0 and the
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//timer stops decrementing
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_irqEnabled = false;
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CPU::SetIRQSource(IRQSource::External);
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}
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}
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}
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_audioChannels[0].Clock();
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_audioChannels[1].Clock();
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}
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void UpdateWorkRamState()
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{
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SetCpuMemoryMapping(0x6000, 0x7FFF, 0, PrgMemoryType::WorkRam, _wramWriteEnabled ? MemoryAccessType::ReadWrite : MemoryAccessType::Read);
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}
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virtual uint8_t MapperReadVRAM(uint16_t addr, MemoryOperationType memoryOperationType) override
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{
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if(_extAttributesEnabled && memoryOperationType == MemoryOperationType::PpuRenderingRead) {
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if(addr >= 0x2000 && (addr & 0x3FF) < 0x3C0) {
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//Nametable fetches
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_lastNametableFetchAddr = addr & 0x03FF;
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} else if(addr >= 0x2000 && (addr & 0x3FF) >= 0x3C0) {
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//Attribute fetches
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uint8_t bank;
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switch(GetMirroringType()) {
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case MirroringType::ScreenAOnly: bank = 0; break;
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case MirroringType::ScreenBOnly: bank = 1; break;
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case MirroringType::Horizontal: bank = (addr & 0x800) ? 1 : 0; break;
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case MirroringType::Vertical: bank = (addr & 0x400) ? 1 : 0; break;
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}
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//Return a byte containing the same palette 4 times - this allows the PPU to select the right palette no matter the shift value
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uint8_t value = _extendedAttributes[bank][_lastNametableFetchAddr & 0x3FF] & 0x03;
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return (value << 6) | (value << 4) | (value << 2) | value;
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}
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}
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return BaseMapper::MapperReadVRAM(addr, memoryOperationType);
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}
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uint8_t ReadRegister(uint16_t addr) override
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{
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switch(addr & 0x5800) {
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case 0x4800: return (_dipSwitch ? 0x80 : 0) | 0x64;
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case 0x5000: return _audioChannels[0].ReadRegister();
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case 0x5800: return _audioChannels[1].ReadRegister();
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}
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return 0;
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}
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void WriteRegister(uint16_t addr, uint8_t value) override
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{
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if(addr <= 0xBFFF) {
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switch(addr & 0x800F) {
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case 0x8000: case 0x8001: case 0x8002: case 0x8003:
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_audioChannels[0].WriteRegister(addr, value);
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break;
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case 0x8004: case 0x8005: case 0x8006: case 0x8007:
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_audioChannels[1].WriteRegister(addr, value);
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break;
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case 0x8008:
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_lowByteIrqCounter = value;
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break;
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case 0x8009:
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//Data written to the IRQ Counter Low register is buffered until writing to IRQ
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//Counter High, at which point the composite data is written directly to the IRQ timer.
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_irqCounter = ((value & 0x7F) << 8) | _lowByteIrqCounter;
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_irqEnabled = (value & 0x80) != 0;
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//Writing to the IRQ Enable register will acknowledge the interrupt and return the /IRQ signal to logic 1.
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CPU::ClearIRQSource(IRQSource::External);
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break;
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case 0x800A:
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switch(value & 0x03) {
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case 0: SetMirroringType(MirroringType::Vertical); break;
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case 1: SetMirroringType(MirroringType::Horizontal); break;
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case 2: SetMirroringType(MirroringType::ScreenAOnly); break;
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case 3: SetMirroringType(MirroringType::ScreenBOnly); break;
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}
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_extAttributesEnabled = (value & 0x04) != 0;
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_wramWriteEnabled = (value & 0x08) != 0;
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UpdateWorkRamState();
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break;
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case 0x800B: SelectPRGPage(0, value & 0x0F); break;
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case 0x800C: SelectCHRPage(0, value & 0x0F); break;
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case 0x800D: SelectCHRPage(1, value & 0x0F); break;
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case 0x800E: SelectCHRPage(2, value & 0x0F); break;
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case 0x800F: SelectCHRPage(3, value & 0x0F); break;
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}
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} else {
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//Attribute expansion memory at $C000-$C7FF is mirrored throughout $C000-$FFFF.
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_extendedAttributes[(addr & 0x400) ? 1 : 0][addr & 0x3FF] = value;
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}
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}
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};
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135
Core/UnlDripGameAudio.h
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135
Core/UnlDripGameAudio.h
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@ -0,0 +1,135 @@
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#include "BaseExpansionAudio.h"
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class UnlDripGameAudio : public BaseExpansionAudio
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{
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private:
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uint8_t _buffer[256];
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uint8_t _readPos;
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uint8_t _writePos;
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bool _bufferFull;
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bool _bufferEmpty;
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uint16_t _freq;
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uint16_t _timer;
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uint8_t _volume;
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int16_t _prevOutput;
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protected:
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void StreamState(bool saving) override
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{
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BaseExpansionAudio::StreamState(saving);
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ArrayInfo<uint8_t> buffer { _buffer, 256 };
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Stream(_readPos, _writePos, _bufferFull, _bufferEmpty, _freq, _timer, _volume, _prevOutput, buffer);
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}
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void ClockAudio() override
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{
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if(_bufferEmpty) {
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return;
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}
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_timer--;
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if(_timer == 0) {
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//Each time the timer reaches zero, it is reloaded and a byte is removed from the
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//channel's FIFO and is output (with 0x80 being the 'center' voltage) at the
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//channel's specified volume.
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_timer = _freq;
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if(_readPos == _writePos) {
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_bufferFull = false;
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}
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_readPos++;
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SetOutput(((int)_buffer[_readPos] - 0x80) * _volume);
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if(_readPos == _writePos) {
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_bufferEmpty = true;
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}
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}
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}
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void SetOutput(int16_t output)
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{
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APU::AddExpansionAudioDelta(AudioChannel::VRC7, (output - _prevOutput) * 3);
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_prevOutput = output;
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}
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void ResetBuffer()
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{
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memset(_buffer, 0, 256);
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_readPos = 0;
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_writePos = 0;
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_bufferFull = false;
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_bufferEmpty = true;
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}
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public:
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UnlDripGameAudio()
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{
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_freq = 0;
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_timer = 0;
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_volume = 0;
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_prevOutput = 0;
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ResetBuffer();
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}
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uint8_t ReadRegister()
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{
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uint8_t result = 0;
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if(_bufferFull) {
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result |= 0x80;
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}
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if(_bufferEmpty) {
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result |= 0x40;
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}
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return result;
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}
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void WriteRegister(uint16_t addr, uint8_t value)
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{
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switch(addr & 0x03) {
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case 0:
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//Writing any value will silence the corresponding sound channel
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//When a channel's Clear FIFO register is written to, its timer is reset to the
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//last written frequency and it is silenced, outputting a 'center' voltage.
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ResetBuffer();
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SetOutput(0);
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_timer = _freq;
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break;
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case 1:
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//Writing a value will insert it into the FIFO.
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if(_readPos == _writePos) {
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//When data is written to an empty channel's Data Port, the channel's timer is
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//reloaded from the Period registers and playback begins immediately.
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_bufferEmpty = false;
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SetOutput((value - 0x80) * _volume);
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_timer = _freq;
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}
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_buffer[_writePos++] = value;
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if(_readPos == _writePos) {
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_bufferFull = true;
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}
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break;
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case 2:
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//Specifies channel playback rate, in cycles per sample (lower 8 bits)
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_freq = (_freq & 0x0F00) | value;
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break;
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case 3:
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//Specifies channel playback rate, in cycles per sample (higher 8 bits) (bits 0-3)
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//Specifies channel playback volume (bits 4-7)
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_freq = (_freq & 0xFF) | ((value & 0x0F) << 8);
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_volume = (value & 0xF0) >> 4;
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if(!_bufferEmpty) {
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//Updates to a channel's Period do not take effect until the current
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//sample has finished playing, but updates to a channel's Volume take effect immediately.
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SetOutput(((int)_buffer[_readPos] - 0x80) * _volume);
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}
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break;
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}
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}
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};
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