5 commits

Author	SHA1	Message	Date
Sour	5b80d2fe21	Core: Changed CPU cycle counter to be a 64-bit int (breaks save state compatibility)	2019-05-12 12:28:01 -04:00
Sour	76f64b19ef	Debugger: Added access counters for CHR ROM/RAM and nametable memory ... +Added read/write highlighting, etc. for memory viewer tabs +Improved show tile/attribute updates in PPU viewer	2019-01-13 18:32:27 -05:00
Sour	859f7e912f	Debugger: Memory Viewer - Added option to highlight breakpoints (by drawing a border around them)	2019-01-03 14:27:10 -05:00
Sour	3defa304c6	Debugger: Added highlight color customization to memory viewer	2017-12-26 17:55:08 -05:00
Sour	c12122d69c	Debugger: Added highlight modes based on CDL flags to memory viewer	2017-12-26 17:33:46 -05:00