b01c2d3f83
This was caused by an old fix for MMC3 save states (AfterLoadState) that is no longer needed (because using SetCpuMemoryMapping no longer requires manually restoring the state)
312 lines
No EOL
8.3 KiB
C++
312 lines
No EOL
8.3 KiB
C++
#pragma once
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#include "stdafx.h"
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#include "BaseMapper.h"
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#include "CPU.h"
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#include "EmulationSettings.h"
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#include "A12Watcher.h"
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class MMC3 : public BaseMapper
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{
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private:
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enum class MMC3Registers
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{
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Reg8000 = 0x8000,
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Reg8001 = 0x8001,
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RegA000 = 0xA000,
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RegA001 = 0xA001,
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RegC000 = 0xC000,
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RegC001 = 0xC001,
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RegE000 = 0xE000,
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RegE001 = 0xE001
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};
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uint8_t _currentRegister;
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bool _wramEnabled;
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bool _wramWriteProtected;
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A12Watcher _a12Watcher;
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bool _needIrq;
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bool _forceMmc3RevAIrqs;
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struct Mmc3State {
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uint8_t Reg8000;
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uint8_t RegA000;
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uint8_t RegA001;
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} _state;
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bool IsMcAcc()
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{
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return _romInfo.MapperID == 4 && _romInfo.SubMapperID == 3;
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}
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protected:
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uint8_t _irqReloadValue;
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uint8_t _irqCounter;
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bool _irqReload;
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bool _irqEnabled;
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uint8_t _prgMode;
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uint8_t _chrMode;
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uint8_t _registers[8];
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uint8_t GetCurrentRegister()
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{
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return _currentRegister;
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}
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Mmc3State GetState()
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{
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return _state;
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}
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uint8_t GetChrMode()
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{
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return _chrMode;
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}
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void ResetMmc3()
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{
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_state.Reg8000 = GetPowerOnByte();
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_state.RegA000 = GetPowerOnByte();
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_state.RegA001 = GetPowerOnByte();
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_chrMode = GetPowerOnByte() & 0x01;
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_prgMode = GetPowerOnByte() & 0x01;
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_currentRegister = GetPowerOnByte();
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_registers[0] = GetPowerOnByte(0);
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_registers[1] = GetPowerOnByte(2);
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_registers[2] = GetPowerOnByte(4);
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_registers[3] = GetPowerOnByte(5);
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_registers[4] = GetPowerOnByte(6);
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_registers[5] = GetPowerOnByte(7);
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_registers[6] = GetPowerOnByte(0);
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_registers[7] = GetPowerOnByte(1);
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_irqCounter = GetPowerOnByte();
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_irqReloadValue = GetPowerOnByte();
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_irqReload = GetPowerOnByte() & 0x01;
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_irqEnabled = GetPowerOnByte() & 0x01;
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_wramEnabled = GetPowerOnByte() & 0x01;
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_wramWriteProtected = GetPowerOnByte() & 0x01;
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_needIrq = false;
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}
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virtual bool ForceMmc3RevAIrqs() { return _forceMmc3RevAIrqs; }
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virtual void UpdateMirroring()
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{
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if(GetMirroringType() != MirroringType::FourScreens) {
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SetMirroringType(((_state.RegA000 & 0x01) == 0x01) ? MirroringType::Horizontal : MirroringType::Vertical);
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}
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}
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virtual void UpdateChrMapping()
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{
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if(_chrMode == 0) {
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SelectCHRPage(0, _registers[0] & 0xFE);
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SelectCHRPage(1, _registers[0] | 0x01);
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SelectCHRPage(2, _registers[1] & 0xFE);
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SelectCHRPage(3, _registers[1] | 0x01);
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SelectCHRPage(4, _registers[2]);
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SelectCHRPage(5, _registers[3]);
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SelectCHRPage(6, _registers[4]);
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SelectCHRPage(7, _registers[5]);
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} else if(_chrMode == 1) {
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SelectCHRPage(0, _registers[2]);
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SelectCHRPage(1, _registers[3]);
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SelectCHRPage(2, _registers[4]);
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SelectCHRPage(3, _registers[5]);
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SelectCHRPage(4, _registers[0] & 0xFE);
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SelectCHRPage(5, _registers[0] | 0x01);
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SelectCHRPage(6, _registers[1] & 0xFE);
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SelectCHRPage(7, _registers[1] | 0x01);
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}
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}
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virtual void UpdatePrgMapping()
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{
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if(_prgMode == 0) {
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SelectPRGPage(0, _registers[6]);
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SelectPRGPage(1, _registers[7]);
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SelectPRGPage(2, -2);
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SelectPRGPage(3, -1);
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} else if(_prgMode == 1) {
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SelectPRGPage(0, -2);
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SelectPRGPage(1, _registers[7]);
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SelectPRGPage(2, _registers[6]);
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SelectPRGPage(3, -1);
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}
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}
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bool CanWriteToWorkRam()
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{
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return _wramEnabled && !_wramWriteProtected;
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}
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virtual void UpdateState()
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{
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_currentRegister = _state.Reg8000 & 0x07;
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_chrMode = (_state.Reg8000 & 0x80) >> 7;
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_prgMode = (_state.Reg8000 & 0x40) >> 6;
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if(_romInfo.MapperID == 4 && _romInfo.SubMapperID == 1) {
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//bool wramEnabled = (_state.Reg8000 & 0x20) == 0x20;
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RemoveCpuMemoryMapping(0x6000, 0x7000);
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uint8_t firstBankAccess = (_state.RegA001 & 0x10 ? MemoryAccessType::Write : 0) | (_state.RegA001 & 0x20 ? MemoryAccessType::Read : 0);
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uint8_t lastBankAccess = (_state.RegA001 & 0x40 ? MemoryAccessType::Write : 0) | (_state.RegA001 & 0x80 ? MemoryAccessType::Read : 0);
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for(int i = 0; i < 4; i++) {
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SetCpuMemoryMapping(0x7000 + i * 0x400, 0x71FF + i * 0x400, 0, PrgMemoryType::SaveRam, firstBankAccess);
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SetCpuMemoryMapping(0x7200 + i * 0x400, 0x73FF + i * 0x400, 1, PrgMemoryType::SaveRam, lastBankAccess);
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}
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} else {
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_wramEnabled = (_state.RegA001 & 0x80) == 0x80;
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_wramWriteProtected = (_state.RegA001 & 0x40) == 0x40;
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if(_romInfo.SubMapperID == 0) {
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if(_wramEnabled) {
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SetCpuMemoryMapping(0x6000, 0x7FFF, 0, HasBattery() ? PrgMemoryType::SaveRam : PrgMemoryType::WorkRam, CanWriteToWorkRam() ? MemoryAccessType::ReadWrite : MemoryAccessType::Read);
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} else {
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RemoveCpuMemoryMapping(0x6000, 0x7FFF);
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}
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}
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}
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UpdatePrgMapping();
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UpdateChrMapping();
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}
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virtual void StreamState(bool saving) override
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{
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BaseMapper::StreamState(saving);
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ArrayInfo<uint8_t> registers = { _registers, 8 };
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SnapshotInfo a12Watcher{ &_a12Watcher };
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Stream(_state.Reg8000, _state.RegA000, _state.RegA001, _currentRegister, _chrMode, _prgMode,
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_irqReloadValue, _irqCounter, _irqReload, _irqEnabled, a12Watcher,
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_wramEnabled, _wramWriteProtected, registers, _needIrq);
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}
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virtual uint16_t GetPRGPageSize() override { return 0x2000; }
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virtual uint16_t GetCHRPageSize() override { return 0x0400; }
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virtual uint32_t GetSaveRamPageSize() override { return _romInfo.SubMapperID == 1 ? 0x200 : 0x2000; }
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virtual uint32_t GetSaveRamSize() override { return _romInfo.SubMapperID == 1 ? 0x400 : 0x2000; }
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virtual void InitMapper() override
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{
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//Force MMC3A irqs for boards that are known to use the A revision.
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//Some MMC3B boards also have the A behavior, but currently no way to tell them apart.
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_forceMmc3RevAIrqs = _romInfo.DatabaseInfo.Chip.substr(0, 5).compare("MMC3A") == 0;
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ResetMmc3();
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SetCpuMemoryMapping(0x6000, 0x7FFF, 0, HasBattery() ? PrgMemoryType::SaveRam : PrgMemoryType::WorkRam);
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UpdateState();
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UpdateMirroring();
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}
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virtual void WriteRegister(uint16_t addr, uint8_t value) override
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{
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switch((MMC3Registers)(addr & 0xE001)) {
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case MMC3Registers::Reg8000:
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_state.Reg8000 = value;
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UpdateState();
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break;
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case MMC3Registers::Reg8001:
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if(_currentRegister <= 1) {
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//"Writes to registers 0 and 1 always ignore bit 0"
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value &= ~0x01;
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}
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_registers[_currentRegister] = value;
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UpdateState();
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break;
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case MMC3Registers::RegA000:
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_state.RegA000 = value;
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UpdateMirroring();
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break;
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case MMC3Registers::RegA001:
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_state.RegA001 = value;
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UpdateState();
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break;
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case MMC3Registers::RegC000:
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_irqReloadValue = value;
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break;
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case MMC3Registers::RegC001:
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_irqCounter = 0;
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_irqReload = true;
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break;
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case MMC3Registers::RegE000:
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_irqEnabled = false;
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_console->GetCpu()->ClearIrqSource(IRQSource::External);
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break;
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case MMC3Registers::RegE001:
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_irqEnabled = true;
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break;
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}
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}
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virtual void TriggerIrq()
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{
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if(IsMcAcc()) {
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//MC-ACC (Acclaim copy of the MMC3)
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//IRQ will be triggered on the next falling edge of A12 instead of on the rising edge like normal MMC3 behavior
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//This adds a 4 ppu cycle delay (until the PPU fetches the next garbage NT tile between sprites)
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_needIrq = true;
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} else {
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_console->GetCpu()->SetIrqSource(IRQSource::External);
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}
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}
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public:
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virtual void NotifyVRAMAddressChange(uint16_t addr) override
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{
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switch(_a12Watcher.UpdateVramAddress(addr, _console->GetPpu()->GetFrameCycle())) {
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case A12StateChange::None:
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break;
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case A12StateChange::Fall:
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if(_needIrq) {
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//Used by MC-ACC (Acclaim copy of the MMC3), see TriggerIrq above
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_console->GetCpu()->SetIrqSource(IRQSource::External);
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_needIrq = false;
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}
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break;
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case A12StateChange::Rise:
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uint32_t count = _irqCounter;
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if(_irqCounter == 0 || _irqReload) {
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_irqCounter = _irqReloadValue;
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} else {
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_irqCounter--;
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}
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//SubMapper 2 = MC-ACC (Acclaim MMC3 clone)
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if(!IsMcAcc() && (ForceMmc3RevAIrqs() || _console->GetSettings()->CheckFlag(EmulationFlags::Mmc3IrqAltBehavior))) {
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//MMC3 Revision A behavior
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if((count > 0 || _irqReload) && _irqCounter == 0 && _irqEnabled) {
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TriggerIrq();
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}
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} else {
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if(_irqCounter == 0 && _irqEnabled) {
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TriggerIrq();
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}
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}
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_irqReload = false;
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break;
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}
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}
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}; |