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Merge pull request #625 from ops/VIAFIX

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VIC-20: Add missing VIA register names
This commit is contained in:
Oliver Schmidt 2018-04-18 17:09:35 +02:00 • committed by GitHub
commit 53df4da8e8
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3 changed files with 45 additions and 19 deletions
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45
asminc/vic20.inc
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@ -66,16 +66,43 @@ VIC_COLOR := $900F ; Border and background color
; ---------------------------------------------------------------------------
; I/O: 6522 VIA1
VIA1 := $9110
VIA1_JOY := $9111
VIA1_DDRB := $9112
VIA1_DDRA := $9113
VIA1 := $9110 ; VIA1 base address
VIA1_JOY := VIA1+$0 ; *** Deprecated ***
VIA1_PB := VIA1+$0 ; Port register B
VIA1_PA1 := VIA1+$1 ; Port register A
VIA1_DDRB := VIA1+$2 ; Data direction register B
VIA1_DDRA := VIA1+$3 ; Data direction register A
VIA1_T1CL := VIA1+$4 ; Timer 1, low byte
VIA1_T1CH := VIA1+$5 ; Timer 1, high byte
VIA1_T1LL := VIA1+$6 ; Timer 1 latch, low byte
VIA1_T1LH := VIA1+$7 ; Timer 1 latch, high byte
VIA1_T2CL := VIA1+$8 ; Timer 2, low byte
VIA1_T2CH := VIA1+$9 ; Timer 2, high byte
VIA1_SR := VIA1+$A ; Shift register
VIA1_CR := VIA1+$B ; Auxiliary control register
VIA1_PCR := VIA1+$C ; Peripheral control register
VIA1_IFR := VIA1+$D ; Interrupt flag register
VIA1_IER := VIA1+$E ; Interrupt enable register
VIA1_PA2 := VIA1+$F ; Port register A w/o handshake
; ---------------------------------------------------------------------------
; I/O: 6522 VIA2
VIA2 := $9120
VIA2_JOY := $9120
VIA2_DDRB := $9122
VIA2_DDRA := $9123
VIA2 := $9120 ; VIA2 base address
VIA2_JOY := VIA2+$0 ; *** Deprecated ***
VIA2_PB := VIA2+$0 ; Port register B
VIA2_PA1 := VIA2+$1 ; Port register A
VIA2_DDRB := VIA2+$2 ; Data direction register B
VIA2_DDRA := VIA2+$3 ; Data direction register A
VIA2_T1CL := VIA2+$4 ; Timer 1, low byte
VIA2_T1CH := VIA2+$5 ; Timer 1, high byte
VIA2_T1LL := VIA2+$6 ; Timer 1 latch, low byte
VIA2_T1LH := VIA2+$7 ; Timer 1 latch, high byte
VIA2_T2CL := VIA2+$8 ; Timer 2, low byte
VIA2_T2CH := VIA2+$9 ; Timer 2, high byte
VIA2_SR := VIA2+$A ; Shift register
VIA2_CR := VIA2+$B ; Auxiliary control register
VIA2_PCR := VIA2+$C ; Peripheral control register
VIA2_IFR := VIA2+$D ; Interrupt flag register
VIA2_IER := VIA2+$E ; Interrupt enable register
VIA2_PA2 := VIA2+$F ; Port register A w/o handshake

15
libsrc/vic20/joy/vic20-ptvjoy.s
View file

@ -40,7 +40,6 @@
; ------------------------------------------------------------------------
; Constants
VIA1_PRB := VIA1 ; User port register
JOY_COUNT = 3 ; Number of joysticks we support
@ -91,13 +90,13 @@ joy1: lda #$7F ; mask for VIA2 JOYBIT: sw3
ldy VIA2_DDRB ; remember the date of DDRB
sta VIA2_DDRB ; set JOYBITS on this VIA for input
lda VIA2_JOY ; read JOYBIT: sw3
lda VIA2_PB ; read JOYBIT: sw3
sty VIA2_DDRB ; restore the state of DDRB
asl ; Shift sw3 into carry
ldy VIA1_DDRA ; remember the state of DDRA
stx VIA1_DDRA ; set JOYBITS on this VIA for input
lda VIA1_JOY ; read JOYBITS: sw0,sw1,sw2,sw4
lda VIA1_PA1 ; read JOYBITS: sw0,sw1,sw2,sw4
sty VIA1_DDRA ; restore the state of DDRA
cli ; necessary?
@ -127,9 +126,9 @@ joy2: lda #%10000000 ; via port B Data-Direction
bne joy3
lda #$80 ; via port B read/write
sta VIA1_PRB ; (output one at PB7)
sta VIA1_PB ; (output one at PB7)
lda VIA1_PRB ; via port B read/write
lda VIA1_PB ; via port B read/write
and #$1F ; get bit 4-0 (PB4-PB0)
eor #$1F
rts
@ -137,13 +136,13 @@ joy2: lda #%10000000 ; via port B Data-Direction
; Read joystick 3
joy3: lda #$00 ; via port B read/write
sta VIA1_PRB ; (output zero at PB7)
sta VIA1_PB ; (output zero at PB7)
lda VIA1_PRB ; via port B read/write
lda VIA1_PB ; via port B read/write
and #$0F ; get bit 3-0 (PB3-PB0)
sta tmp1 ; joy 4 directions
lda VIA1_PRB ; via port B read/write
lda VIA1_PB ; via port B read/write
and #%00100000 ; get bit 5 (PB5)
lsr
ora tmp1

4
libsrc/vic20/joy/vic20-stdjoy.s
View file

@ -90,13 +90,13 @@ READ: lda #$7F ; mask for VIA2 JOYBIT: sw3
ldy VIA2_DDRB ; remember the date of DDRB
sta VIA2_DDRB ; set JOYBITS on this VIA for input
lda VIA2_JOY ; read JOYBIT: sw3
lda VIA2_PB ; read JOYBIT: sw3
sty VIA2_DDRB ; restore the state of DDRB
asl ; Shift sw3 into carry
ldy VIA1_DDRA ; remember the state of DDRA
stx VIA1_DDRA ; set JOYBITS on this VIA for input
lda VIA1_JOY ; read JOYBITS: sw0,sw1,sw2,sw4
lda VIA1_PA1 ; read JOYBITS: sw0,sw1,sw2,sw4
sty VIA1_DDRA ; restore the state of DDRA
cli ; necessary?