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fixed issues found by gregg

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This commit is contained in:
mrdudz 2015-07-15 13:18:12 +02:00
parent ac27ed301a
commit c3d45e4c47
8 changed files with 76 additions and 99 deletions
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21
asminc/pce.inc
View file

@ -42,6 +42,9 @@ VDC_DESR =16 ; (DMA) Destination Register
VDC_LENR =17 ; (DMA) Length Register
VDC_SATB =18 ; Sprite Attribute Table
; VDC port
; Note: absolute addressing mode must be used when writing to this port
VDC_CTRL = $0000
VDC_DATA_LO = $0002
VDC_DATA_HI = $0003
@ -79,24 +82,6 @@ IRQ_STATUS = $1403
CDR_MEM_DISABLE = $1803
CDR_MEM_ENABLE = $1807
;; lda abs
.macro ldaio arg1
.byte $ad
.word arg1
.endmacro
;; sta abs
.macro staio arg1
.byte $8d
.word arg1
.endmacro
;; stz abs
.macro stzio arg1
.byte $9c
.word arg1
.endmacro
; Write VDC register
.macro VREG arg1,arg2
st0 #arg1

3
include/pce.h
View file

@ -65,9 +65,6 @@
#define COLOR_LIGHTBLUE 0x0E
#define COLOR_GRAY3 0x0F
#define CLOCKS_PER_SEC 50 // FIXME: is this correct?
#define CLK_TCK 50 // FIXME: is this correct?
#define TV_NTSC 0
#define TV_PAL 1
#define TV_OTHER 2

4
include/time.h
View file

@ -99,6 +99,10 @@ unsigned _clocks_per_sec (void);
#elif defined(__NES__)
# define CLK_TCK 50 /* POSIX */
# define CLOCKS_PER_SEC 50 /* ANSI */
#elif defined(__PCE__)
/* FIXME: we likely need to read it at runtime */
# define CLK_TCK 50 /* POSIX */
# define CLOCKS_PER_SEC 50 /* ANSI */
#elif defined(__GEOS__)
# define CLK_TCK 1 /* POSIX */
# define CLOCKS_PER_SEC 1 /* ANSI */

8
libsrc/pce/clrscr.s
View file

@ -11,10 +11,10 @@ _clrscr:
st0 #VDC_VWR
ldy #$40
rowloop: ldx #$80
colloop: lda #' '
staio VDC_DATA_LO
lda #$02
staio VDC_DATA_HI
colloop: lda #' '
sta a:VDC_DATA_LO
lda #$02
sta a:VDC_DATA_HI
dex
bne colloop

24
libsrc/pce/conio.s
View file

@ -4,8 +4,6 @@
.import psg_init
.import vdc_init
.export initconio
.constructor initconio, 24
.macpack longbranch
@ -28,17 +26,19 @@ set_palette:
ldx #0
@lp:
.repeat 16
lda colors,x
ldy #16
@lp1:
lda colors,x
sta VCE_DATA_LO
lda colors+1,x
lda colors+1,x
sta VCE_DATA_HI
.endrepeat
dey
bne @lp1
inx
inx
cpx #16*2
jne @lp
cpx #16*2
jne @lp
stz VCE_ADDR_LO
stz VCE_ADDR_HI
@ -68,9 +68,9 @@ conio_init:
ldy #$80 ; 128 chars
charloop: ldx #$08 ; 8 bytes/char
lineloop:
lda (ptr1)
staio VDC_DATA_LO ; bitplane 0
stzio VDC_DATA_HI ; bitplane 1
lda (ptr1)
sta a:VDC_DATA_LO ; bitplane 0
stz a:VDC_DATA_HI ; bitplane 1
clc ; increment font pointer
lda ptr1
@ -89,7 +89,7 @@ fillloop: st1 #$00
dey
bne charloop ; next character
ldx #0
ldx #0
stx BGCOLOR
inx
stx CHARCOLOR

21
libsrc/pce/cputc.s
View file

@ -69,26 +69,25 @@ putchar:
st0 #VDC_MAWR ; Memory Adress Write
lda SCREEN_PTR
staio VDC_DATA_LO
sta a:VDC_DATA_LO
lda SCREEN_PTR+1
staio VDC_DATA_HI
sta a:VDC_DATA_HI
st0 #VDC_VWR ; VWR
txa
staio VDC_DATA_LO ; character
sta a:VDC_DATA_LO ; character
lda CHARCOLOR
lda CHARCOLOR
asl a
asl a
asl a
asl a
asl a
asl a
asl a
asl a
and #$f0
ora #$02
staio VDC_DATA_HI
ora #$02
sta a:VDC_DATA_HI
rts

84
libsrc/pce/crt0.s
View file

@ -30,11 +30,6 @@
.importzp sp
.importzp ptr1,ptr2
; ------------------------------------------------------------------------
; Create an empty LOWCODE segment to avoid linker warnings
.segment "LOWCODE"
; ------------------------------------------------------------------------
; Place the startup code in a special segment.
@ -42,7 +37,7 @@
start:
; setup the CPU and System-IRQ
; setup the CPU and System-IRQ
; Initialize CPU
@ -96,58 +91,55 @@ start:
cli
; Clear the BSS data
jsr zerobss
jsr zerobss
; Copy the .data segment to RAM
lda #<(__DATA_LOAD__)
sta ptr1
lda #>(__DATA_LOAD__)
sta ptr1+1
lda #<(__DATA_RUN__)
sta ptr2
lda #>(__DATA_RUN__)
sta ptr2+1
lda #<(__DATA_LOAD__)
sta ptr1
lda #>(__DATA_LOAD__)
sta ptr1+1
lda #<(__DATA_RUN__)
sta ptr2
lda #>(__DATA_RUN__)
sta ptr2+1
ldx #>(__DATA_SIZE__)
ldx #>(__DATA_SIZE__)
@l2:
beq @s1 ; no more full pages
beq @s1 ; no more full pages
; copy one page
ldy #0
ldy #0
@l1:
lda (ptr1),y
sta (ptr2),y
lda (ptr1),y
sta (ptr2),y
iny
bne @l1
bne @l1
inc ptr1+1
inc ptr2+1
inc ptr1+1
inc ptr2+1
dex
bne @l2
bne @l2
; copy remaining bytes
@s1:
; copy one page
ldy #0
ldy #0
@l3:
lda (ptr1),y
sta (ptr2),y
lda (ptr1),y
sta (ptr2),y
iny
cpy #<(__DATA_SIZE__)
bne @l3
cpy #<(__DATA_SIZE__)
bne @l3
; setup the stack
lda #<(__RAM_START__+__RAM_SIZE__)
sta sp
lda #>(__RAM_START__+__RAM_SIZE__)
sta sp+1
; Init the Heap
jsr initheap
lda #<(__RAM_START__+__RAM_SIZE__)
sta sp
lda #>(__RAM_START__+__RAM_SIZE__)
sta sp+1
; Call module constructors
jsr initlib
jsr initlib
; Pass an empty command line
jsr push0 ; argc
@ -158,7 +150,7 @@ start:
; Call module destructors. This is also the _exit entry.
_exit:
jsr donelib ; Run module destructors
jsr donelib ; Run module destructors
; reset the PCEngine (start over)
jmp start
@ -174,16 +166,16 @@ _irq1:
phy
inc tickcount
bne @s1
inc tickcount+1
bne @s1
inc tickcount+2
bne @s1
inc tickcount+3
inc tickcount
bne @s1
inc tickcount+1
bne @s1
inc tickcount+2
bne @s1
inc tickcount+3
@s1:
; Acknowlege interrupt
ldaio VDC_CTRL
lda a:VDC_CTRL
ply
plx

10
libsrc/pce/vdc.s
View file

@ -6,7 +6,7 @@ HIRES = 1
.export vdc_init
vdc_init:
ldaio VDC_CTRL
lda a:VDC_CTRL
VREG $00, $0000 ; MAWR
VREG $01, $0000 ; MARR
@ -20,21 +20,21 @@ vdc_init:
VREG $0E, $000C ; CRTC - VDE
VREG $0F, $0000 ; DCR
.if HIRES
.if HIRES
VREG $0A, $0C02 ; CRTC - HSR
VREG $0B, $043C ; CRTC - HDS
lda #$06
sta VCE_CTRL
.else
.else
VREG $0A, $0202 ; CRTC - HSR
VREG $0B, $041F ; CRTC - HDS
lda #$04
sta VCE_CTRL
.endif
.endif
ldaio VDC_CTRL
lda a:VDC_CTRL
rts