Merge remote-tracking branch 'upstream/master' into ntsc
This commit is contained in:
Andrea Odetti
commit
6f0a71a330
9 changed files with 113 additions and 37 deletions
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@ -9,12 +9,19 @@ https://github.com/AppleWin/AppleWin/issues/new
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Tom Charlesworth
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1.29.5.0 - 11 Nov 2019
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1.29.6.0 - 18 Nov 2019
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----------------------
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. [Bug #724] Fixed so that 6502 interrupt is delayed by 1 opcode when interrupt occurs on last cycle of opcode.
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- fixes French Touch's "Mad Effect" & "Mad Effect #2" demos.
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. [Bug #711] Fixed Mockingboard initial "stretched" music playback (regression introduced at 1.28.7.0).
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. [Bug #707] Fixed ADTPro (running under AppleWin) not working with real COM ports.
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. [Bug #701] Fixed 6522's TIMER being out-of-sync with 6502.
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. [Bug #699] Fixed French Touch's "Mad Effect". See #656, #701, #724.
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. [Bug #680] Fixed video tearing (eg. for FT's "Scroll Scroll Scroll" & "Mad Effect #2").
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. [Bug #659] Fix for Applied Engineering's Phasor song player (noisy playback) (regression introduced at 1.26.3.4).
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. [Bug #656] Changed so only TEXT ($C050/1) and MIXED ($C052/3) have a 1 cycle delay (extension to 1.28.8.0).
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- fixes French Touch's "Mad Effect" demo.
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- fixed Deater's "Cycle-count Megademo" (vertical GR grey line shouldn't be visible between GR & HGR video).
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. [Bug #652] Fixed 6522's TIMER to underflow at 0x0000 -> 0xFFFF
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- and T1C=0x0000 now correctly underflows on next cycle.
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. [Bug #435] COM ports above COM9 weren't available from the UI.
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@ -23,6 +30,7 @@ Tom Charlesworth
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. [PR #694] Debugger: Symbol loading: Fix random crash upon start up.
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. Fixed crash with debug command line switches: -m and -no-mb.
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(1.29.5.0 - skipped)
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1.29.4.0 - 24 Oct 2019
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----------------------
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@ -1,4 +1,4 @@
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#define APPLEWIN_VERSION 1,29,5,0
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#define APPLEWIN_VERSION 1,29,6,0
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#define xstr(a) str(a)
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#define str(a) #a
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@ -143,6 +143,8 @@ static volatile UINT32 g_bmIRQ = 0;
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static volatile UINT32 g_bmNMI = 0;
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static volatile BOOL g_bNmiFlank = FALSE; // Positive going flank on NMI line
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static bool g_irqDefer1Opcode = false;
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//
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static eCpuType g_MainCPU = CPU_65C02;
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@ -403,10 +405,23 @@ static __forceinline void NMI(ULONG& uExecutedCycles, BOOL& flagc, BOOL& flagn,
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#endif
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}
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// NB. No need to save to save-state, as IRQ() follows CheckInterruptSources(), and IRQ() always sets it to false.
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static bool g_irqOnLastOpcodeCycle = false;
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static __forceinline void IRQ(ULONG& uExecutedCycles, BOOL& flagc, BOOL& flagn, BOOL& flagv, BOOL& flagz)
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{
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if(g_bmIRQ && !(regs.ps & AF_INTERRUPT))
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{
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// if 6522 interrupt occurs on opcode's last cycle, then defer IRQ by 1 opcode
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if (g_irqOnLastOpcodeCycle && !g_irqDefer1Opcode)
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{
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g_irqOnLastOpcodeCycle = false;
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g_irqDefer1Opcode = true; // if INT occurs again on next opcode, then do NOT defer
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return;
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}
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g_irqDefer1Opcode = false;
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// IRQ signals are deasserted when a specific r/w operation is done on device
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#ifdef _DEBUG
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g_nCycleIrqStart = g_nCumulativeCycles + uExecutedCycles;
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@ -420,6 +435,8 @@ static __forceinline void IRQ(ULONG& uExecutedCycles, BOOL& flagc, BOOL& flagn,
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UINT uExtraCycles = 0; // Needed for CYC(a) macro
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CYC(7)
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}
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g_irqOnLastOpcodeCycle = false;
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}
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const int IRQ_CHECK_OPCODE_FULL_SPEED = 40; // ~128 cycles (assume 3 cycles per opcode)
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@ -435,7 +452,9 @@ static __forceinline void CheckInterruptSources(ULONG uExecutedCycles, const boo
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g_fullSpeedOpcodeCount = IRQ_CHECK_OPCODE_FULL_SPEED;
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}
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MB_UpdateCycles(uExecutedCycles);
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if (MB_UpdateCycles(uExecutedCycles))
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g_irqOnLastOpcodeCycle = true;
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if (sg_Mouse.IsActive())
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sg_Mouse.SetVBlank( !VideoGetVblBar(uExecutedCycles) );
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}
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@ -536,11 +555,10 @@ DWORD CpuExecute(const DWORD uCycles, const bool bVideoUpdate)
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// >0 : Do multi-opcode emulation
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const DWORD uExecutedCycles = InternalCpuExecute(uCycles, bVideoUpdate);
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// NB. Required for normal-speed (even though 6522 is updated after every opcode), as may've finished on IRQ()
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MB_UpdateCycles(uExecutedCycles); // Update 6522s (NB. Do this before updating g_nCumulativeCycles below)
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// NB. Ensures that 6522 regs are up-to-date for any potential save-state
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//
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const UINT nRemainingCycles = uExecutedCycles - g_nCyclesExecuted;
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g_nCumulativeCycles += nRemainingCycles;
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@ -665,6 +683,8 @@ void CpuReset()
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regs.bJammed = 0;
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g_irqDefer1Opcode = false;
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SetActiveCpu( GetMainCpu() );
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z80_reset();
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}
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@ -678,7 +698,8 @@ void CpuReset()
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#define SS_YAML_KEY_REGP "P"
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#define SS_YAML_KEY_REGS "S"
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#define SS_YAML_KEY_REGPC "PC"
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#define SS_YAML_KEY_CUMULATIVECYCLES "Cumulative Cycles"
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#define SS_YAML_KEY_CUMULATIVE_CYCLES "Cumulative Cycles"
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#define SS_YAML_KEY_IRQ_DEFER_1_OPCODE "Defer IRQ By 1 Opcode"
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#define SS_YAML_VALUE_6502 "6502"
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#define SS_YAML_VALUE_65C02 "65C02"
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@ -701,10 +722,11 @@ void CpuSaveSnapshot(YamlSaveHelper& yamlSaveHelper)
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yamlSaveHelper.SaveHexUint8(SS_YAML_KEY_REGP, regs.ps);
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yamlSaveHelper.SaveHexUint8(SS_YAML_KEY_REGS, (BYTE) regs.sp);
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yamlSaveHelper.SaveHexUint16(SS_YAML_KEY_REGPC, regs.pc);
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yamlSaveHelper.SaveHexUint64(SS_YAML_KEY_CUMULATIVECYCLES, g_nCumulativeCycles);
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yamlSaveHelper.SaveHexUint64(SS_YAML_KEY_CUMULATIVE_CYCLES, g_nCumulativeCycles);
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yamlSaveHelper.SaveBool(SS_YAML_KEY_IRQ_DEFER_1_OPCODE, g_irqDefer1Opcode);
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}
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void CpuLoadSnapshot(YamlLoadHelper& yamlLoadHelper)
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void CpuLoadSnapshot(YamlLoadHelper& yamlLoadHelper, UINT version)
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{
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if (!yamlLoadHelper.GetSubMap(CpuGetSnapshotStructName()))
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return;
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@ -725,7 +747,10 @@ void CpuLoadSnapshot(YamlLoadHelper& yamlLoadHelper)
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CpuIrqReset();
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CpuNmiReset();
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g_nCumulativeCycles = yamlLoadHelper.LoadUint64(SS_YAML_KEY_CUMULATIVECYCLES);
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g_nCumulativeCycles = yamlLoadHelper.LoadUint64(SS_YAML_KEY_CUMULATIVE_CYCLES);
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if (version >= 5)
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g_irqDefer1Opcode = yamlLoadHelper.LoadBool(SS_YAML_KEY_IRQ_DEFER_1_OPCODE);
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yamlLoadHelper.PopMap();
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}
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@ -29,7 +29,7 @@ void CpuNmiAssert(eIRQSRC Device);
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void CpuNmiDeassert(eIRQSRC Device);
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void CpuReset ();
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void CpuSaveSnapshot(class YamlSaveHelper& yamlSaveHelper);
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void CpuLoadSnapshot(class YamlLoadHelper& yamlLoadHelper);
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void CpuLoadSnapshot(class YamlLoadHelper& yamlLoadHelper, UINT version);
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BYTE CpuRead(USHORT addr, ULONG uExecutedCycles);
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void CpuWrite(USHORT addr, BYTE a, ULONG uExecutedCycles);
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@ -129,6 +129,10 @@ struct SY6522_AY8910
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SSI263A SpeechChip;
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MockingboardUnitState_e state; // Where a unit is a 6522+AY8910 pair
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MockingboardUnitState_e stateB; // Phasor: 6522 & 2nd AY8910
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// NB. No need to save to save-state, as it will be done immediately after opcode completes in MB_UpdateCycles()
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bool bLoadT1C; // Load T1C with T1L after opcode completes
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bool bLoadT2C; // Load T2C with T2L after opcode completes
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};
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@ -433,7 +437,7 @@ static void SY6522_Write(BYTE nDevice, BYTE nReg, BYTE nValue)
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UpdateIFR(pMB, IxR_TIMER1);
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pMB->sy6522.TIMER1_LATCH.h = nValue;
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pMB->sy6522.TIMER1_COUNTER.w = pMB->sy6522.TIMER1_LATCH.w;
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pMB->bLoadT1C = true;
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StartTimer1(pMB);
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CpuAdjustIrqCheck(pMB->sy6522.TIMER1_LATCH.w); // Sync IRQ check timeout with 6522 counter underflow - GH#608
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@ -529,7 +533,8 @@ static BYTE SY6522_Read(BYTE nDevice, BYTE nReg)
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nValue = pMB->sy6522.DDRA;
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break;
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case 0x04: // TIMER1L_COUNTER
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nValue = pMB->sy6522.TIMER1_COUNTER.l;
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// NB. GH#701 (T1C:=0xFFFF, LDA T1C_L, A==0xFC)
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nValue = (pMB->sy6522.TIMER1_COUNTER.w - 3) & 0xff; // -3 to compensate for the (assumed) 4-cycle STA 6522.T1C_H
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UpdateIFR(pMB, IxR_TIMER1);
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break;
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case 0x05: // TIMER1H_COUNTER
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@ -1541,7 +1546,8 @@ void MB_Reset() // CTRL+RESET or power-cycle
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static BYTE __stdcall MB_Read(WORD PC, WORD nAddr, BYTE bWrite, BYTE nValue, ULONG nExecutedCycles)
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{
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MB_UpdateCycles(nExecutedCycles);
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if (g_bFullSpeed)
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MB_UpdateCycles(nExecutedCycles);
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#ifdef _DEBUG
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if(!IS_APPLE2 && MemCheckINTCXROM())
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@ -1604,7 +1610,8 @@ static BYTE __stdcall MB_Read(WORD PC, WORD nAddr, BYTE bWrite, BYTE nValue, ULO
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static BYTE __stdcall MB_Write(WORD PC, WORD nAddr, BYTE bWrite, BYTE nValue, ULONG nExecutedCycles)
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{
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MB_UpdateCycles(nExecutedCycles);
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if (g_bFullSpeed)
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MB_UpdateCycles(nExecutedCycles);
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#ifdef _DEBUG
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if(!IS_APPLE2 && MemCheckINTCXROM())
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@ -1794,6 +1801,9 @@ void MB_PeriodicUpdate(UINT executedCycles)
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static bool CheckTimerUnderflowAndIrq(USHORT& timerCounter, int& timerIrqDelay, const USHORT nClocks, bool* pTimerUnderflow=NULL)
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{
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if (nClocks == 0)
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return false;
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int oldTimer = timerCounter;
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int timer = timerCounter;
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timer -= nClocks;
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@ -1803,23 +1813,21 @@ static bool CheckTimerUnderflowAndIrq(USHORT& timerCounter, int& timerIrqDelay,
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if (timerIrqDelay) // Deal with any previous counter underflow which didn't yet result in an IRQ
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{
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timerIrqDelay -= nClocks;
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if (timerIrqDelay <= 0)
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{
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timerIrqDelay = 0;
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timerIrq = true;
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}
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// don't re-underflow if TIMER = 0xFFFF or 0xFFFE (so just return)
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_ASSERT(timerIrqDelay == 1);
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timerIrqDelay = 0;
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timerIrq = true;
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// if LATCH is very small then could underflow for every opcode...
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}
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else if (oldTimer >= 0 && timer < 0) // Underflow occurs for 0x0000 -> 0xFFFF
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if (oldTimer >= 0 && timer < 0) // Underflow occurs for 0x0000 -> 0xFFFF
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{
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if (pTimerUnderflow)
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*pTimerUnderflow = true; // Just for Willy Byte!
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if (timer < -2)
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if (timer <= -2) // TIMER = 0xFFFE (or less)
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timerIrq = true;
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else // TIMER = 0xFFFF or 0xFFFE
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timerIrqDelay = 3 + timer; // ...so 2 or 1 cycles until IRQ
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else // TIMER = 0xFFFF
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timerIrqDelay = 1; // ...so 1 cycle until IRQ
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}
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return timerIrq;
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@ -1828,24 +1836,45 @@ static bool CheckTimerUnderflowAndIrq(USHORT& timerCounter, int& timerIrqDelay,
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// Called by:
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// . CpuExecute() every ~1000 @ 1MHz
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// . CheckInterruptSources() every opcode (or every 40 opcodes at full-speed)
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// . MB_Read() / MB_Write()
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void MB_UpdateCycles(ULONG uExecutedCycles)
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// . MB_Read() / MB_Write() (only for full-speed)
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bool MB_UpdateCycles(ULONG uExecutedCycles)
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{
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if (g_SoundcardType == CT_Empty)
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return;
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return false;
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CpuCalcCycles(uExecutedCycles);
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UINT64 uCycles = g_nCumulativeCycles - g_uLastCumulativeCycles;
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if (uCycles == 0)
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return false; // Likely when called from CpuExecute()
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_ASSERT(uCycles > 1);
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const bool isOpcode = (uCycles > 1 && uCycles <= 7); // todo: better to pass in a flag?
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g_uLastCumulativeCycles = g_nCumulativeCycles;
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_ASSERT(uCycles < 0x10000);
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USHORT nClocks = (USHORT) uCycles;
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bool bIrqOnLastOpcodeCycle = false;
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for (int i=0; i<NUM_SY6522; i++)
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{
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SY6522_AY8910* pMB = &g_MB[i];
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bool bTimer1Underflow = false; // Just for Willy Byte!
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const bool bTimer1Irq = CheckTimerUnderflowAndIrq(pMB->sy6522.TIMER1_COUNTER.w, pMB->sy6522.timer1IrqDelay, nClocks, &bTimer1Underflow);
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bool bTimer1Irq = false;
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bool bTimer1IrqOnLastCycle = false;
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if (isOpcode)
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{
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bTimer1Irq = CheckTimerUnderflowAndIrq(pMB->sy6522.TIMER1_COUNTER.w, pMB->sy6522.timer1IrqDelay, nClocks-1, &bTimer1Underflow);
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bTimer1IrqOnLastCycle = CheckTimerUnderflowAndIrq(pMB->sy6522.TIMER1_COUNTER.w, pMB->sy6522.timer1IrqDelay, 1, &bTimer1Underflow);
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bTimer1Irq = bTimer1Irq || bTimer1IrqOnLastCycle;
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}
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else
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{
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bTimer1Irq = CheckTimerUnderflowAndIrq(pMB->sy6522.TIMER1_COUNTER.w, pMB->sy6522.timer1IrqDelay, nClocks, &bTimer1Underflow);
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}
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const bool bTimer2Irq = CheckTimerUnderflowAndIrq(pMB->sy6522.TIMER2_COUNTER.w, pMB->sy6522.timer2IrqDelay, nClocks);
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if (!pMB->bTimer1Active && bTimer1Underflow)
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@ -1864,6 +1893,7 @@ void MB_UpdateCycles(ULONG uExecutedCycles)
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if (pMB->bTimer1Active && bTimer1Irq)
|
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{
|
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UpdateIFR(pMB, 0, IxR_TIMER1);
|
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bIrqOnLastOpcodeCycle = true;
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MB_Update();
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@ -1880,6 +1910,9 @@ void MB_UpdateCycles(ULONG uExecutedCycles)
|
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// - Ultima4/5 change ACCESS_TIMER1 after a couple of IRQs into tune
|
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pMB->sy6522.TIMER1_COUNTER.w += pMB->sy6522.TIMER1_LATCH.w; // GH#651: account for underflowed cycles too
|
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pMB->sy6522.TIMER1_COUNTER.w += 2; // GH#652: account for extra 2 cycles (Rockwell, Fig.16: period=N+2cycles)
|
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// EG. T1C=0xFFFE, T1L=0x0001
|
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// . T1C += T1L = 0xFFFF
|
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// . T1C += 2 = 0x0001
|
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if (pMB->sy6522.TIMER1_COUNTER.w > pMB->sy6522.TIMER1_LATCH.w)
|
||||
{
|
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if (pMB->sy6522.TIMER1_LATCH.w)
|
||||
|
|
@ -1891,6 +1924,12 @@ void MB_UpdateCycles(ULONG uExecutedCycles)
|
|||
}
|
||||
}
|
||||
|
||||
if (pMB->bLoadT1C)
|
||||
{
|
||||
pMB->bLoadT1C = false;
|
||||
pMB->sy6522.TIMER1_COUNTER.w = pMB->sy6522.TIMER1_LATCH.w;
|
||||
}
|
||||
|
||||
if (pMB->bTimer2Active && bTimer2Irq)
|
||||
{
|
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UpdateIFR(pMB, 0, IxR_TIMER2);
|
||||
|
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@ -1913,6 +1952,8 @@ void MB_UpdateCycles(ULONG uExecutedCycles)
|
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}
|
||||
}
|
||||
}
|
||||
|
||||
return bIrqOnLastOpcodeCycle;
|
||||
}
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ void MB_Demute();
|
|||
void MB_StartOfCpuExecute();
|
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void MB_PeriodicUpdate(UINT executedCycles);
|
||||
void MB_CheckIRQ();
|
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void MB_UpdateCycles(ULONG uExecutedCycles);
|
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bool MB_UpdateCycles(ULONG uExecutedCycles);
|
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SS_CARDTYPE MB_GetSoundcardType();
|
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bool MB_IsActive();
|
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DWORD MB_GetVolume();
|
||||
|
|
|
|||
|
|
@ -116,7 +116,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|||
static int g_nHiresPage = 1;
|
||||
static int g_nTextPage = 1;
|
||||
|
||||
static bool g_bDelayVideoMode = false;
|
||||
static bool g_bDelayVideoMode = false; // NB. No need to save to save-state, as it will be done immediately after opcode completes in NTSC_VideoUpdateCycles()
|
||||
static uint32_t g_uNewVideoModeFlags = 0;
|
||||
|
||||
// Understanding the Apple II, Timing Generation and the Video Scanner, Pg 3-11
|
||||
|
|
|
|||
|
|
@ -68,7 +68,8 @@ static YamlHelper yamlHelper;
|
|||
// v2: Extended: keyboard (added 'Key Waiting'), memory (LC mem type for II/II+, inverted MF_INTCXROM bit)
|
||||
// v3: Extended: memory (added 'AnnunciatorN')
|
||||
// v4: Extended: video (added 'Video Refresh Rate')
|
||||
#define UNIT_APPLE2_VER 4
|
||||
// v5: Extended: cpu (added 'Defer IRQ By 1 Opcode')
|
||||
#define UNIT_APPLE2_VER 5
|
||||
|
||||
#define UNIT_SLOTS_VER 1
|
||||
|
||||
|
|
@ -214,7 +215,7 @@ static void ParseUnitApple2(YamlLoadHelper& yamlLoadHelper, UINT version)
|
|||
SetApple2Type( ParseApple2Type(model) ); // NB. Sets default main CPU type
|
||||
m_ConfigNew.m_Apple2Type = GetApple2Type();
|
||||
|
||||
CpuLoadSnapshot(yamlLoadHelper); // NB. Overrides default main CPU type
|
||||
CpuLoadSnapshot(yamlLoadHelper, version); // NB. Overrides default main CPU type
|
||||
m_ConfigNew.m_CpuType = GetMainCpu();
|
||||
|
||||
JoyLoadSnapshot(yamlLoadHelper);
|
||||
|
|
@ -390,7 +391,7 @@ static void Snapshot_LoadState_v2(void)
|
|||
m_ConfigNew.m_bEnableHDD = false;
|
||||
//m_ConfigNew.m_bEnableTheFreezesF8Rom = ?; // todo: when support saving config
|
||||
|
||||
MemReset();
|
||||
MemReset(); // Also calls CpuInitialize()
|
||||
PravetsReset();
|
||||
sg_Disk2Card.Reset();
|
||||
HD_Reset();
|
||||
|
|
|
|||
|
|
@ -660,9 +660,10 @@ BYTE VideoSetMode(WORD, WORD address, BYTE write, BYTE, ULONG uExecutedCycles)
|
|||
if (!IS_APPLE2)
|
||||
RGB_SetVideoMode(address);
|
||||
|
||||
bool delay = true;
|
||||
if ((oldVideoMode ^ g_uVideoMode) & VF_PAGE2)
|
||||
delay = false; // PAGE2 flag changed state, so no 1 cycle delay (GH#656)
|
||||
// Only 1-cycle delay for VF_TEXT & VF_MIXED mode changes (GH#656)
|
||||
bool delay = false;
|
||||
if ((oldVideoMode ^ g_uVideoMode) & (VF_TEXT|VF_MIXED))
|
||||
delay = true;
|
||||
|
||||
NTSC_SetVideoMode( g_uVideoMode, delay );
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue