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HDMA: Fixed timings on HDMA initalization (and fixed regression that caused DRAM refresh to not longer occur)

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This commit is contained in:
Sour 2019-03-26 19:07:06 -04:00
parent c7326e626f
commit 53de61ba90
2 changed files with 13 additions and 15 deletions
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6
Core/DmaController.cpp
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@ -114,10 +114,10 @@ void DmaController::InitHdmaChannels()
ch.TransferSize = (msb << 8) | lsb;
//"and 24 master cycles for each channel set for indirect HDMA"
_memoryManager->IncrementMasterClockValue<24>();
_memoryManager->IncrementMasterClockValue<16>();
} else {
//"plus 8 master cycles for each channel set for direct HDMA"
_memoryManager->IncrementMasterClockValue<8>();
_memoryManager->IncrementMasterClockValue<4>();
}
//4. Set DoTransfer to true.
@ -216,7 +216,7 @@ void DmaController::ProcessHdmaChannels()
}
//"If a new indirect address is required, 16 master cycles are taken to load it."
_memoryManager->IncrementMasterClockValue<8>(); //minus 8 before the ReadDmas call will increment it by 4 twice
_memoryManager->IncrementMasterClockValue<8>(); //minus 8 because the ReadDmas call will increment it by 4 twice
}
//"c. If $43xA is zero, terminate this HDMA channel for this frame. The bit in $420c is not cleared, though, so it may be automatically restarted next frame."

22
Core/Ppu.cpp
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@ -164,19 +164,17 @@ void Ppu::Exec()
}
}
if(_scanline <= (_overscanMode ? 239 : 224)) {
if(_cycle == 278) {
if(_scanline != 0) {
RenderScanline();
}
if(!_forcedVblank) {
EvaluateNextLineSprites();
_console->GetDmaController()->ProcessHdmaChannels();
}
} else if(_scanline == 0 && _cycle == 6) {
//TODO : To verify: Do HDMA channels get initialized even in forced blank?
_console->GetDmaController()->InitHdmaChannels();
if(_cycle == 278 && _scanline <= (_overscanMode ? 239 : 224)) {
if(_scanline != 0) {
RenderScanline();
}
if(!_forcedVblank) {
EvaluateNextLineSprites();
_console->GetDmaController()->ProcessHdmaChannels();
}
} else if(_scanline == 0 && _cycle == 6) {
//TODO : To verify: Do HDMA channels get initialized even in forced blank?
_console->GetDmaController()->InitHdmaChannels();
} else if((_cycle == 134 || _cycle == 135) && (_console->GetMemoryManager()->GetMasterClock() & 0x07) == 0) {
//TODO Approximation (DRAM refresh timing is not exact)
_console->GetMemoryManager()->IncrementMasterClockValue<40>();