NovaSquirrel
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c0e249e993
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Revert "Merge branch 'reformat_code'"
This reverts commit daf3b57e89, reversing
changes made to 7a6e0b7d77.
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2021-03-10 11:13:28 -05:00 |
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Vladimir Kononovich
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3764af908f
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Reformat Core (Resharper)
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2020-12-19 23:30:09 +03:00 |
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Sour
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884aa1abcc
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Minor performance improvements (5-15%)
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2020-06-24 18:43:49 -04:00 |
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Sour
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71d0ac693a
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Debugger: Improved GSU disassembly/debugger
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2020-02-23 15:58:14 -05:00 |
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Sour
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9aba01ba0c
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Added cheat code support (GG & PAR)
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2019-10-12 22:40:25 -04:00 |
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Sour
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33cee67e61
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Added GSU (Super FX) support
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2019-07-30 22:43:32 -04:00 |
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Sour
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fe470dd87a
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SA-1 support (still missing a few rarely used features)
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2019-07-25 22:22:09 -04:00 |
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Sour
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add1523e31
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Refactor code for memory mappings
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2019-07-15 18:30:13 -04:00 |
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Sour
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95d0c5a910
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Fixed some uninitialized variables
+ Fixed rare crash when calling Stop()
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2019-07-13 13:43:56 -04:00 |
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Sour
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1f18728acb
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Fixed console components leaking when power cycling
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2019-07-13 00:02:51 -04:00 |
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Sour
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d46c8c3fa4
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Refactored master clock code to improve performance
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2019-07-12 23:55:18 -04:00 |
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Sour
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5d79229f3a
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CPU: Added cycle-by-cycle emulation for mul & div registers
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2019-07-06 09:29:35 -04:00 |
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Sour
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6dd2862482
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Fixed compilation warning
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2019-04-20 21:54:51 -04:00 |
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Sour
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e203d40e6f
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IRQ: Fixed regression that caused IRQs on H=0 to never fire
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2019-04-20 18:52:07 -04:00 |
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Sour
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7bc96a867d
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Performance improvements and refactoring for timing changes
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2019-04-20 14:17:34 -04:00 |
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Sour
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984b1be481
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Timing improvements (DMA, HDMA, DRAM refresh, CPU cycles)
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2019-04-20 14:17:32 -04:00 |
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Sour
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8dee056dda
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DMA: Improved DMA/HDMA timing
Wait 1 cpu cycle before starting then sync to the next multiple of 8 and sync back to a multiple of a CPU cycle before stopping
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2019-04-11 22:34:28 -04:00 |
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Sour
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f8392d2f65
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Debugger: SPC trace logging
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2019-04-06 17:38:14 -04:00 |
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Sour
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e1c7e7b9c4
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Linux: Fixed build/makefile and compilation errors/warnings (and add missing files to git)
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2019-03-31 14:50:12 -04:00 |
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Sour
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41ee29d650
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Debugger: Improved memory tools performance
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2019-03-28 22:45:01 -04:00 |
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Sour
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bb0c8b1f10
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DMA: Fix behavior when trying to write to B bus registers using the A bus (and when trying to read/write DMA registers using DMA) + fixed DMA wrapping when it reaches the end of a bank
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2019-03-16 16:36:58 -04:00 |
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Sour
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63f6de6a8e
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Core: Reset/Power Cycle support (+ fixed power on state for DMA controller)
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2019-03-16 12:20:18 -04:00 |
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Sour
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73913e1f0c
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Save state support
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2019-03-12 09:15:57 -04:00 |
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Sour
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a018f1129a
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DMA: Restrict $2080<->WRAM DMA behavior based on tests
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2019-03-09 14:27:32 -05:00 |
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Sour
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348da3879b
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Core: Open bus improvements
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2019-03-09 00:31:54 -05:00 |
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Sour
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7211eece7c
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CPU/PPU: Improved timings
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2019-03-08 10:27:16 -05:00 |
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Sour
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0ada7f9d2f
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Debugger: Added Event Viewer
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2019-03-07 20:12:32 -05:00 |
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Sour
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4139f6dca8
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CPU/PPU: Improved timing and implemented catch-up in PPU when registers are written to in the middle of a scanline
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2019-03-04 17:49:14 -05:00 |
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Sour
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c9eb9cef52
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Debugger: Show effective address/memory value in disassembly + update trace logger to use the same code
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2019-02-28 16:53:04 -05:00 |
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Sour
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4ee2c42663
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Memory manager refactoring
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2019-02-26 22:27:09 -05:00 |
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Sour
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853821de2f
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Cart: Save/load .srm save ram files
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2019-02-24 20:04:59 -05:00 |
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Sour
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02425d7453
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DMA: Added delay values for DMA/HDMA
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2019-02-21 23:35:51 -05:00 |
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Sour
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0b7ad7c0db
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CPU: Added all idle cycles + added DRAM refresh delay
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2019-02-21 22:10:41 -05:00 |
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Sour
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97c7d06156
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Fixed throw syntax
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2019-02-21 18:18:25 -05:00 |
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Sour
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170a33af49
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CPU: Implemented FastROM register
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2019-02-21 18:12:44 -05:00 |
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Sour
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b2af226467
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Code optimization
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2019-02-21 17:17:55 -05:00 |
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Sour
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5952fcd3f5
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DMA: Implemented DMA register reads
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2019-02-21 07:55:53 -05:00 |
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Sour
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68e7617c95
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PPU: Implemented VRAM/CGRAM reads + H/V offset data latches
+ Implemented work ram read register
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2019-02-21 07:27:47 -05:00 |
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Sour
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221bc44700
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DMA: Added support for HDMA (incorrect timings)
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2019-02-19 21:09:12 -05:00 |
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Sour
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b806b3d96e
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Core: Added SNES controller support
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2019-02-17 20:29:29 -05:00 |
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Sour
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aaf147b53b
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Refactor internal CPU registers + implement division register
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2019-02-17 15:37:31 -05:00 |
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Sour
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93e8fd9d5e
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Core: Fixed for memory mappings, implemented multiplication register, added logging to help debugging missing functionalities
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2019-02-17 14:42:35 -05:00 |
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Sour
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bdc57286e7
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SPC: Integrate blargg's SPC emulation library
Sound still doesn't work, however.
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2019-02-16 11:23:01 -05:00 |
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Sour
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e257db4def
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Fixed memory leaks
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2019-02-16 01:16:57 -05:00 |
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Sour
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6d22b920b8
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Debugger: Added hex editor
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2019-02-15 21:33:13 -05:00 |
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Sour
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0f657ccf63
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DMA: Refactoring + improvements/fixes
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2019-02-15 00:08:50 -05:00 |
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Sour
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b33380a95e
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CPU: Fixed bugs with PEA/PEI/PER
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2019-02-14 19:00:17 -05:00 |
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Sour
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69cf69fa6f
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PPU: Implement some of the registers
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2019-02-13 18:44:39 -05:00 |
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Sour
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522372a365
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Fixed addressing bugs, added PPU stub, improved trace logger output, split CPU instructions to another file
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2019-02-13 13:32:51 -05:00 |
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Sour
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5c19584019
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Imported some code from Mesen (video, audio, UI, etc.) + basic trace logger/step functionality
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2019-02-12 22:13:09 -05:00 |
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