empathicqubit/Mesen-SX
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923 commits 3 branches 4 tags 18 MiB
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38 commits

Author SHA1 Message Date
NovaSquirrel
47000bd6a5 Add readable/writable byte at $43xB and $43xF 2020-10-06 01:04:38 -04:00
Sour
01dd319c9a HDMA: Added missing condition for indirect HDMA glitch 
Fixes Touge Densetsu color corruption in bike configuration screen
 2020-06-10 18:08:08 -04:00
Sour
0ed96a0432 IRQ: Tweaked IRQ/WAI timings 
+ Check enabled hdma channels on dot 276 (rather than the CPU cycle following dot 276)
Fixes Full Throttle & ASP graphical issues
Also gets hdmaen_latch tests closer to what they should be
(Unsure if this is accurate or not, though)
 2020-01-18 13:12:15 -05:00
Sour
af175616cd Debugger: Added Register Viewer tool 2019-10-10 23:54:38 -04:00
Sour
fe470dd87a SA-1 support (still missing a few rarely used features) 2019-07-25 22:22:09 -04:00
Sour
f720c39215 Fixed some clang/gcc warnings 2019-07-18 16:54:24 -04:00
Sour
d46c8c3fa4 Refactored master clock code to improve performance 2019-07-12 23:55:18 -04:00
Sour
3f4a72a338 CPU: Reset D & DBR to 0 on reset (fixes SG&G freeze on reset) 
+ Generally fix reset behavior for the 65816 based on available info
 2019-07-08 22:03:58 -04:00
Sour
3e8abac530 DMA: Fixed HDMA not properly interrupting DMA (fixes Dekitate High School) 
Also fixed timing inaccuracies and refactored a bit.
 2019-07-06 18:07:09 -04:00
Sour
2927939a56 DMA: Implemented cpu cycle that skips the IRQ/NMI check after DMA 2019-07-05 19:18:30 -04:00
Sour
66c3d0a3b1 CPU: Fixed pre/post-DMA timings when writing to $420B 
i.e: read next opcode pre-DMA, finish that instruction post-DMA
 2019-06-30 19:47:12 -04:00
Sour
886234aae5 Debugger: Event Viewer - Added DMA channel filters and more DMA-related information to the tooltips 2019-05-04 20:13:31 -04:00
Sour
7bc96a867d Performance improvements and refactoring for timing changes 2019-04-20 14:17:34 -04:00
Sour
984b1be481 Timing improvements (DMA, HDMA, DRAM refresh, CPU cycles) 2019-04-20 14:17:32 -04:00
Sour
8dee056dda DMA: Improved DMA/HDMA timing 
Wait 1 cpu cycle before starting then sync to the next multiple of 8 and sync back to a multiple of a CPU cycle before stopping
 2019-04-11 22:34:28 -04:00
Sour
7bb0910607 HDMA: Set DoTransfer flag to true for all 8 HDMA channels during init if at least 1 HDMA channel is active (Fixed "Ladida_lol" test) 2019-04-11 20:08:19 -04:00
Sour
260e0f089d DMA: Implement NMI/IRQ handler delay after DMA/HDMA 2019-04-04 17:49:47 -04:00
Sour
e1c7e7b9c4 Linux: Fixed build/makefile and compilation errors/warnings (and add missing files to git) 2019-03-31 14:50:12 -04:00
Sour
53de61ba90 HDMA: Fixed timings on HDMA initalization (and fixed regression that caused DRAM refresh to not longer occur) 2019-03-26 19:07:06 -04:00
Sour
664c984a9d HDMA: Decrement flag is ignored for HDMA transfers 2019-03-25 18:29:37 -04:00
Sour
273403676a HDMA: No overhead for HDMA if all channels are disabled (?) 2019-03-22 21:37:31 -04:00
Sour
bb0c8b1f10 DMA: Fix behavior when trying to write to B bus registers using the A bus (and when trying to read/write DMA registers using DMA) + fixed DMA wrapping when it reaches the end of a bank 2019-03-16 16:36:58 -04:00
Sour
63f6de6a8e Core: Reset/Power Cycle support (+ fixed power on state for DMA controller) 2019-03-16 12:20:18 -04:00
Sour
73913e1f0c Save state support 2019-03-12 09:15:57 -04:00
Sour
a018f1129a DMA: Restrict $2080<->WRAM DMA behavior based on tests 2019-03-09 14:27:32 -05:00
Sour
2cecde26fb DMA: HDMA init/run must interrupt/cancel regular DMA 2019-03-09 12:01:36 -05:00
Sour
7211eece7c CPU/PPU: Improved timings 2019-03-08 10:27:16 -05:00
Sour
0218d57de7 HDMA: FixedTransfer flag does not affect HDMA 2019-03-04 19:46:08 -05:00
Sour
b9321f66f7 DMA: Reset DoTransfer flag when initializing HDMA channels 2019-03-03 13:53:00 -05:00
Sour
c809f096f5 HDMA: Fixed HDMA only working until any channel was disabled/done 2019-02-22 22:15:45 -05:00
Sour
b6b1620e00 DMA: Fixed (?) source bank for HDMA 2019-02-22 18:40:39 -05:00
Sour
02425d7453 DMA: Added delay values for DMA/HDMA 2019-02-21 23:35:51 -05:00
Sour
5952fcd3f5 DMA: Implemented DMA register reads 2019-02-21 07:55:53 -05:00
Sour
221bc44700 DMA: Added support for HDMA (incorrect timings) 2019-02-19 21:09:12 -05:00
Sour
93e8fd9d5e Core: Fixed for memory mappings, implemented multiplication register, added logging to help debugging missing functionalities 2019-02-17 14:42:35 -05:00
Sour
e257db4def Fixed memory leaks 2019-02-16 01:16:57 -05:00
Sour
85c84146bf DMA: Implemented all dma transfer modes 2019-02-16 00:47:02 -05:00
Sour
0f657ccf63 DMA: Refactoring + improvements/fixes 2019-02-15 00:08:50 -05:00