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MMC5 - Fixed a few bugs

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This commit is contained in:
Souryo 2015-08-18 18:02:40 -04:00
parent 199e1f1527
commit ad085f1a75
2 changed files with 18 additions and 6 deletions
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8
Core/BaseMapper.h
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@ -410,6 +410,8 @@ class BaseMapper : public IMemoryHandler, public Snapshotable, public INotificat
return ReadRegister(addr); return ReadRegister(addr);
} else if(_prgPageAccessType[addr >> 8] & MemoryAccessType::Read) { } else if(_prgPageAccessType[addr >> 8] & MemoryAccessType::Read) {
return _prgPages[addr >> 8][addr & 0xFF]; return _prgPages[addr >> 8][addr & 0xFF];
} else {
//assert(false);
} }
return 0; return 0;
} }
@ -420,6 +422,8 @@ class BaseMapper : public IMemoryHandler, public Snapshotable, public INotificat
WriteRegister(addr, value); WriteRegister(addr, value);
} else if(_prgPageAccessType[addr >> 8] & MemoryAccessType::Write) { } else if(_prgPageAccessType[addr >> 8] & MemoryAccessType::Write) {
_prgPages[addr >> 8][addr & 0xFF] = value; _prgPages[addr >> 8][addr & 0xFF] = value;
} else {
//assert(false);
} }
} }
@ -427,6 +431,8 @@ class BaseMapper : public IMemoryHandler, public Snapshotable, public INotificat
{ {
if(_chrPageAccessType[addr >> 8] & MemoryAccessType::Read) { if(_chrPageAccessType[addr >> 8] & MemoryAccessType::Read) {
return _chrPages[addr >> 8][addr & 0xFF]; return _chrPages[addr >> 8][addr & 0xFF];
} else {
//assert(false);
} }
return 0; return 0;
} }
@ -435,6 +441,8 @@ class BaseMapper : public IMemoryHandler, public Snapshotable, public INotificat
{ {
if(_chrPageAccessType[addr >> 8] & MemoryAccessType::Write) { if(_chrPageAccessType[addr >> 8] & MemoryAccessType::Write) {
_chrPages[addr >> 8][addr & 0xFF] = value; _chrPages[addr >> 8][addr & 0xFF] = value;
} else {
//assert(false);
} }
} }

16
Core/MMC5.h
View file

@ -64,8 +64,8 @@ private:
if((((bankNumber & 0x80) == 0x00) && reg != 0x04) || reg == 0x00) { if((((bankNumber & 0x80) == 0x00) && reg != 0x04) || reg == 0x00) {
bankNumber &= 0x07; bankNumber &= 0x07;
memoryType = PrgMemoryType::SaveRam; memoryType = PrgMemoryType::SaveRam;
uint8_t accessType = MemoryAccessType::Read; accessType = MemoryAccessType::Read;
if(_prgRamProtect1 == 0x10 && _prgRamProtect2 == 0x01) { if(_prgRamProtect1 == 0x02 && _prgRamProtect2 == 0x01) {
accessType |= MemoryAccessType::Write; accessType |= MemoryAccessType::Write;
} }
} else { } else {
@ -246,7 +246,7 @@ private:
protected: protected:
virtual uint16_t GetPRGPageSize() { return 0x2000; } virtual uint16_t GetPRGPageSize() { return 0x2000; }
virtual uint16_t GetCHRPageSize() { return 0x400; } virtual uint16_t GetCHRPageSize() { return 0x400; }
virtual uint16_t RegisterStartAddress() { return 0x5100; } virtual uint16_t RegisterStartAddress() { return 0x5000; }
virtual uint16_t RegisterEndAddress() { return 0x5206; } virtual uint16_t RegisterEndAddress() { return 0x5206; }
virtual uint32_t GetSaveRamSize() { return 0x10000; } //Emulate as if a single 64k block of saved ram existed virtual uint32_t GetSaveRamSize() { return 0x10000; } //Emulate as if a single 64k block of saved ram existed
virtual uint32_t GetSaveRamPageSize() { return 0x2000; } virtual uint32_t GetSaveRamPageSize() { return 0x2000; }
@ -312,9 +312,13 @@ protected:
virtual void WriteRAM(uint16_t addr, uint8_t value) virtual void WriteRAM(uint16_t addr, uint8_t value)
{ {
if(_ppuInFrame && addr >= 0x5C00 && addr <= 0x5FFF && _extendedRamMode <= 1) { if(addr >= 0x5C00 && addr <= 0x5FFF && _extendedRamMode <= 1) {
//Mode 0/1 - Not readable (returns open bus), can only be written while the PPU is rendering (otherwise, 0 is written) PPUControlFlags flags = PPU::GetControlFlags();
value = 0; if(!flags.BackgroundEnabled && !flags.SpritesEnabled) {
//Expansion RAM ($5C00-$5FFF, read/write)
//Mode 0/1 - Not readable (returns open bus), can only be written while the PPU is rendering (otherwise, 0 is written)
value = 0;
}
} }
BaseMapper::WriteRAM(addr, value); BaseMapper::WriteRAM(addr, value);
} }