Sour
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a36a09df32
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CPU: Fixed timing issues with some instructions
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2019-06-30 12:36:15 -04:00 |
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Sour
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984b1be481
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Timing improvements (DMA, HDMA, DRAM refresh, CPU cycles)
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2019-04-20 14:17:32 -04:00 |
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Sour
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401c2c91cb
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CPU: Fixed move behavior with 8-bit index mode
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2019-03-24 20:20:43 -04:00 |
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Sour
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63f6de6a8e
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Core: Reset/Power Cycle support (+ fixed power on state for DMA controller)
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2019-03-16 12:20:18 -04:00 |
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Sour
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98d72d55b5
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Debugger: Added some values to the expression evaluator
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2019-03-09 16:03:48 -05:00 |
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Sour
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f0ce0f63af
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CPU: Improve implementation of STP/WAI instructions
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2019-03-09 11:57:15 -05:00 |
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Sour
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4139f6dca8
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CPU/PPU: Improved timing and implemented catch-up in PPU when registers are written to in the middle of a scanline
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2019-03-04 17:49:14 -05:00 |
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Sour
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e321b247ac
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CPU: Allow move instructions to be interrupted by an IRQ/NMI
+ Implemented WAI instruction
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2019-03-02 10:58:25 -05:00 |
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Sour
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c9eb9cef52
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Debugger: Show effective address/memory value in disassembly + update trace logger to use the same code
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2019-02-28 16:53:04 -05:00 |
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Sour
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0b7ad7c0db
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CPU: Added all idle cycles + added DRAM refresh delay
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2019-02-21 22:10:41 -05:00 |
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Sour
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6e32ebfffd
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CPU: MVN/MVP set the value of DBR to the destination bank
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2019-02-21 00:40:32 -05:00 |
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Sour
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e6809305f1
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CPU: Enabling 8-bit indexes must truncate the value of X/Y (refix)
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2019-02-20 22:46:14 -05:00 |
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Sour
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1a90a36d3c
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CPU: TSC/TDC/TCD always transfer a full 16-bit
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2019-02-20 22:01:04 -05:00 |
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Sour
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0b757f6fad
|
CPU: Fixed MVN/MVP when A is $FFFF
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2019-02-20 20:16:11 -05:00 |
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Sour
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f75db1b297
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CPU: Fixed MVN/MVP instructions using the wrong src/dest banks
|
2019-02-20 20:00:59 -05:00 |
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Sour
|
011caf951c
|
CPU: Enabling 8-bit indexes must truncate the value of X/Y
|
2019-02-20 19:53:45 -05:00 |
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Sour
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ad251609d6
|
CPU: Fixed ADC/SBC instructions (passes blargg's adc/sbc tests)
|
2019-02-18 23:04:08 -05:00 |
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Sour
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eb158131a5
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CPU: MSB of accumulator should not be modified by shift operations when 8-bit memory operations are enabled
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2019-02-18 20:24:17 -05:00 |
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Sour
|
0757ccefa6
|
PPU: Horizontal/vertical IRQ timer support
|
2019-02-17 01:09:47 -05:00 |
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Sour
|
829f4e23c9
|
CPU: Fixed NMI logic/vector & JML instruction ($5C)
|
2019-02-15 00:09:46 -05:00 |
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Sour
|
574a9a6a69
|
CPU: Implemented MVN/MVP
|
2019-02-14 20:11:21 -05:00 |
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Sour
|
b33380a95e
|
CPU: Fixed bugs with PEA/PEI/PER
|
2019-02-14 19:00:17 -05:00 |
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Sour
|
f979d31971
|
CPU: Implement TRB/TSB instructions
|
2019-02-14 07:08:46 -05:00 |
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Sour
|
3cf0b0e46d
|
CPU: BIT with immediate addressing should not alter V/N flags
|
2019-02-14 00:49:34 -05:00 |
|
Sour
|
0f64559882
|
CPU: Fixed issues with OR/EOR/AND and stack addressing mode
|
2019-02-14 00:48:16 -05:00 |
|
Sour
|
930f504861
|
CPU: Fixed transfer instructions (based on CPUTRN test rom)
|
2019-02-13 23:41:00 -05:00 |
|
Sour
|
82010a792f
|
Fixed PHB and XCE instructions
|
2019-02-13 13:33:10 -05:00 |
|
Sour
|
522372a365
|
Fixed addressing bugs, added PPU stub, improved trace logger output, split CPU instructions to another file
|
2019-02-13 13:32:51 -05:00 |
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