Commit graph

30 commits

Author SHA1 Message Date
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28443f84d6 Debugger: Fixed display issues in disassembly view for SA-1 debugger
Effective addresses and their values were incorrect
2020-02-27 19:59:41 -05:00
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73c1a90833 NMI/IRQ: Fixes and refactoring to attempt to better represent the hardware
Fixes Power Rangers - The Fighting Edition having partially corrupted graphics during fights
2019-12-05 22:13:39 -05:00
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fe470dd87a SA-1 support (still missing a few rarely used features) 2019-07-25 22:22:09 -04:00
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5d79229f3a CPU: Added cycle-by-cycle emulation for mul & div registers 2019-07-06 09:29:35 -04:00
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2927939a56 DMA: Implemented cpu cycle that skips the IRQ/NMI check after DMA 2019-07-05 19:18:30 -04:00
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a36a09df32 CPU: Fixed timing issues with some instructions 2019-06-30 12:36:15 -04:00
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984b1be481 Timing improvements (DMA, HDMA, DRAM refresh, CPU cycles) 2019-04-20 14:17:32 -04:00
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02fa095a91 Debugger: Fixed crash when disassembling while CPU is waiting on an interrupt 2019-04-04 23:50:39 -04:00
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260e0f089d DMA: Implement NMI/IRQ handler delay after DMA/HDMA 2019-04-04 17:49:47 -04:00
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e1c7e7b9c4 Linux: Fixed build/makefile and compilation errors/warnings (and add missing files to git) 2019-03-31 14:50:12 -04:00
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ebfd42f5b6 CPU: Improve timings for WAI instruction (?) 2019-03-22 21:37:32 -04:00
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73913e1f0c Save state support 2019-03-12 09:15:57 -04:00
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98d72d55b5 Debugger: Added some values to the expression evaluator 2019-03-09 16:03:48 -05:00
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f0ce0f63af CPU: Improve implementation of STP/WAI instructions 2019-03-09 11:57:15 -05:00
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0ada7f9d2f Debugger: Added Event Viewer 2019-03-07 20:12:32 -05:00
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4139f6dca8 CPU/PPU: Improved timing and implemented catch-up in PPU when registers are written to in the middle of a scanline 2019-03-04 17:49:14 -05:00
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25837e5c71 CPU: Fixed BRK/COP instructions (read + ignore the signature byte) 2019-03-02 20:26:14 -05:00
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c9eb9cef52 Debugger: Show effective address/memory value in disassembly + update trace logger to use the same code 2019-02-28 16:53:04 -05:00
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0b7ad7c0db CPU: Added all idle cycles + added DRAM refresh delay 2019-02-21 22:10:41 -05:00
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e6809305f1 CPU: Enabling 8-bit indexes must truncate the value of X/Y (refix) 2019-02-20 22:46:14 -05:00
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aaf147b53b Refactor internal CPU registers + implement division register 2019-02-17 15:37:31 -05:00
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0757ccefa6 PPU: Horizontal/vertical IRQ timer support 2019-02-17 01:09:47 -05:00
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829f4e23c9 CPU: Fixed NMI logic/vector & JML instruction ($5C) 2019-02-15 00:09:46 -05:00
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f979d31971 CPU: Implement TRB/TSB instructions 2019-02-14 07:08:46 -05:00
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0f64559882 CPU: Fixed issues with OR/EOR/AND and stack addressing mode 2019-02-14 00:48:16 -05:00
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ca95636c37 CPU addressing review/fixes, trace logger improvements 2019-02-13 18:44:12 -05:00
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522372a365 Fixed addressing bugs, added PPU stub, improved trace logger output, split CPU instructions to another file 2019-02-13 13:32:51 -05:00
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5c19584019 Imported some code from Mesen (video, audio, UI, etc.) + basic trace logger/step functionality 2019-02-12 22:13:09 -05:00
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5e7eebe078 CPU: Fixed immediate more 8-bit vs 16-bit logic
+ Added bare minimum logic to load a rom and start executing it
2019-02-11 22:41:34 -05:00
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8ad76f6c31 65816 core working in 6502 emulation mode 2019-02-11 19:18:47 -05:00