Sour
|
72c17966b9
|
WRAM: Fixed out-of-bounds memory access on register reads
|
2019-03-01 19:31:24 -05:00 |
|
Sour
|
27476a08ab
|
Debugger: Fixed disassembly output for PEA/PEI/PER
|
2019-02-28 23:06:26 -05:00 |
|
Sour
|
c9eb9cef52
|
Debugger: Show effective address/memory value in disassembly + update trace logger to use the same code
|
2019-02-28 16:53:04 -05:00 |
|
Sour
|
26e90e90a1
|
Debugger: Watch list
|
2019-02-27 20:33:56 -05:00 |
|
Sour
|
802bd75df1
|
Debugger: Disassembly window, code data logger
|
2019-02-27 19:49:26 -05:00 |
|
Sour
|
4ee2c42663
|
Memory manager refactoring
|
2019-02-26 22:27:09 -05:00 |
|
Sour
|
cc8ddabf88
|
PGO build configuration
|
2019-02-24 23:53:14 -05:00 |
|
Sour
|
853821de2f
|
Cart: Save/load .srm save ram files
|
2019-02-24 20:04:59 -05:00 |
|
Sour
|
069c8dc42d
|
Fixed compilation warnings/errors
|
2019-02-24 19:57:34 -05:00 |
|
Sour
|
002cda8cf6
|
PPU: Sprite interlace flag support (untested)
|
2019-02-24 19:21:19 -05:00 |
|
Sour
|
76d1aa82e5
|
PPU: Fixed obj/color window mask logic not being applied correctly
|
2019-02-24 19:02:21 -05:00 |
|
Sour
|
b9aedafd32
|
PPU: Offset per tile mode support (mode 2/4/6)
|
2019-02-24 18:45:47 -05:00 |
|
Sour
|
5a45665d74
|
PPU: Fixed negative X sprite display logic
|
2019-02-24 13:09:22 -05:00 |
|
Sour
|
66cc7847fb
|
Fixed project issues (DLL was not included in .exe)
+ Prevent crash when SPC bios is not found
|
2019-02-24 12:54:14 -05:00 |
|
Sour
|
75dee8b8e4
|
PPU: Fixed mode 5 when using 16x16 tiles
|
2019-02-24 11:14:24 -05:00 |
|
Sour
|
e80d6fcd7f
|
PPU: Mode 6 support (incomplete)
|
2019-02-24 10:30:19 -05:00 |
|
Sour
|
3aa008b831
|
PPU: Fixed out-of-bounds memory access in mode 7 with negative offsets
|
2019-02-24 10:29:11 -05:00 |
|
Sour
|
0431e1931d
|
PPU: Fixed sprite display when vertical mirroring is enabled
|
2019-02-24 10:02:22 -05:00 |
|
Sour
|
21791170f4
|
PPU: Fixed VRAM read behavior
|
2019-02-24 09:38:22 -05:00 |
|
Sour
|
073e7b2bf3
|
PPU: Code refactoring
|
2019-02-24 01:30:55 -05:00 |
|
Sour
|
16cc0653e9
|
PPU: Direct color mode support
|
2019-02-24 01:11:26 -05:00 |
|
Sour
|
85f1333c3d
|
PPU: Support for mode 5, hires, interlace, and overscan mode
|
2019-02-23 21:39:35 -05:00 |
|
Sour
|
19a6663ed9
|
PPU: Mode 7 Ext BG mode
|
2019-02-23 16:04:04 -05:00 |
|
Sour
|
39ae565aa1
|
PPU: Mode 7 support
|
2019-02-23 15:40:32 -05:00 |
|
Sour
|
86326215fd
|
PPU: Precalculate some flags through templates for performance
|
2019-02-23 08:54:46 -05:00 |
|
Sour
|
fef78e5802
|
PPU: Support for 16x16 tiles
|
2019-02-23 01:28:41 -05:00 |
|
Sour
|
4b2697612e
|
PPU: Minor refactoring
|
2019-02-22 22:35:53 -05:00 |
|
Sour
|
f028518664
|
PPU: Implement brightness control
|
2019-02-22 22:31:20 -05:00 |
|
Sour
|
dbfed2bb46
|
PPU: Implemented color window
|
2019-02-22 22:19:20 -05:00 |
|
Sour
|
c809f096f5
|
HDMA: Fixed HDMA only working until any channel was disabled/done
|
2019-02-22 22:15:45 -05:00 |
|
Sour
|
a009e899a2
|
PPU: Window support (except color window)
|
2019-02-22 20:15:55 -05:00 |
|
Sour
|
7f5d93d680
|
PPU: Minor refactoring
|
2019-02-22 18:41:43 -05:00 |
|
Sour
|
462bffa513
|
UI: Added icon to .exe
|
2019-02-22 18:41:11 -05:00 |
|
Sour
|
b6b1620e00
|
DMA: Fixed (?) source bank for HDMA
|
2019-02-22 18:40:39 -05:00 |
|
Sour
|
02425d7453
|
DMA: Added delay values for DMA/HDMA
|
2019-02-21 23:35:51 -05:00 |
|
Sour
|
596d6b9ce8
|
PPU: Optimizations (runs ~20% faster)
|
2019-02-21 22:40:08 -05:00 |
|
Sour
|
0b7ad7c0db
|
CPU: Added all idle cycles + added DRAM refresh delay
|
2019-02-21 22:10:41 -05:00 |
|
Sour
|
97c7d06156
|
Fixed throw syntax
|
2019-02-21 18:18:25 -05:00 |
|
Sour
|
170a33af49
|
CPU: Implemented FastROM register
|
2019-02-21 18:12:44 -05:00 |
|
Sour
|
bcf41aca83
|
PPU: Implemented second PPU status flag ($213F)
|
2019-02-21 18:11:31 -05:00 |
|
Sour
|
93b730b390
|
PPU: Fixed V/H read toggle
|
2019-02-21 17:45:11 -05:00 |
|
Sour
|
66aa5034a0
|
Core: Added frame limiter
|
2019-02-21 17:18:56 -05:00 |
|
Sour
|
b2af226467
|
Code optimization
|
2019-02-21 17:17:55 -05:00 |
|
Sour
|
a71de2a7bf
|
SPC: Run SPC 1 frame per frame, rather than 60 frames per frame.
+ Fixed warnings in SPC code in 64-bit mode
|
2019-02-21 16:49:19 -05:00 |
|
Sour
|
d73ca5bf82
|
PPU: Implemented multiply register
|
2019-02-21 08:15:00 -05:00 |
|
Sour
|
5952fcd3f5
|
DMA: Implemented DMA register reads
|
2019-02-21 07:55:53 -05:00 |
|
Sour
|
68e7617c95
|
PPU: Implemented VRAM/CGRAM reads + H/V offset data latches
+ Implemented work ram read register
|
2019-02-21 07:27:47 -05:00 |
|
Sour
|
6e32ebfffd
|
CPU: MVN/MVP set the value of DBR to the destination bank
|
2019-02-21 00:40:32 -05:00 |
|
Sour
|
e6809305f1
|
CPU: Enabling 8-bit indexes must truncate the value of X/Y (refix)
|
2019-02-20 22:46:14 -05:00 |
|
Sour
|
1a90a36d3c
|
CPU: TSC/TDC/TCD always transfer a full 16-bit
|
2019-02-20 22:01:04 -05:00 |
|